RE: [PATCH v1 18/22] test/qtest/hace: Update source data and digest data type to 64-bit

[Jamin Lin]

Hi Cédric,

> Subject: Re: [PATCH v1 18/22] test/qtest/hace: Update source data and digest
> data type to 64-bit
> 
> On 3/21/25 10:26, Jamin Lin wrote:
> > Currently, the hash data source and digest result buffer addresses are
> > set to 32-bit. However, the AST2700 CPU is a 64-bit Cortex-A35
> > architecture, and its DRAM base address is also 64-bit.
> >
> > To support AST2700, update the hash data source address and digest
> > result buffer address to use 64-bit addressing.
> >
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> >   tests/qtest/aspeed-hace-utils.h | 20 +++----
> >   tests/qtest/aspeed-hace-utils.c | 96 ++++++++++++++++-----------------
> >   2 files changed, 58 insertions(+), 58 deletions(-)
> >
> > diff --git a/tests/qtest/aspeed-hace-utils.h
> > b/tests/qtest/aspeed-hace-utils.h index f4440561de..0382570fa2 100644
> > --- a/tests/qtest/aspeed-hace-utils.h
> > +++ b/tests/qtest/aspeed-hace-utils.h
> > @@ -51,25 +51,25 @@ struct AspeedMasks {
> >   };
> >
> >   void aspeed_test_md5(const char *machine, const uint32_t base,
> > -                     const uint32_t src_addr);
> > +                     const uint64_t src_addr);
> >   void aspeed_test_sha256(const char *machine, const uint32_t base,
> > -                        const uint32_t src_addr);
> > +                        const uint64_t src_addr);
> >   void aspeed_test_sha384(const char *machine, const uint32_t base,
> > -                        const uint32_t src_addr);
> > +                        const uint64_t src_addr);
> >   void aspeed_test_sha512(const char *machine, const uint32_t base,
> > -                        const uint32_t src_addr);
> > +                        const uint64_t src_addr);
> >   void aspeed_test_sha256_sg(const char *machine, const uint32_t base,
> > -                           const uint32_t src_addr);
> > +                           const uint64_t src_addr);
> >   void aspeed_test_sha384_sg(const char *machine, const uint32_t base,
> > -                           const uint32_t src_addr);
> > +                           const uint64_t src_addr);
> >   void aspeed_test_sha512_sg(const char *machine, const uint32_t base,
> > -                           const uint32_t src_addr);
> > +                           const uint64_t src_addr);
> >   void aspeed_test_sha256_accum(const char *machine, const uint32_t
> base,
> > -                              const uint32_t src_addr);
> > +                              const uint64_t src_addr);
> >   void aspeed_test_sha384_accum(const char *machine, const uint32_t
> base,
> > -                              const uint32_t src_addr);
> > +                              const uint64_t src_addr);
> >   void aspeed_test_sha512_accum(const char *machine, const uint32_t
> base,
> > -                              const uint32_t src_addr);
> > +                              const uint64_t src_addr);
> >   void aspeed_test_addresses(const char *machine, const uint32_t base,
> >                              const struct AspeedMasks *expected);
> >
> > diff --git a/tests/qtest/aspeed-hace-utils.c
> > b/tests/qtest/aspeed-hace-utils.c index d3146898c2..f39bb8ea48 100644
> > --- a/tests/qtest/aspeed-hace-utils.c
> > +++ b/tests/qtest/aspeed-hace-utils.c
> > @@ -153,22 +153,22 @@ static const uint8_t test_result_accum_sha256[] =
> {
> >       0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a,
> 0x9c,
> >       0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad};
> >
> > -static void write_regs(QTestState *s, uint32_t base, uint32_t src,
> > -                       uint32_t length, uint32_t out, uint32_t method)
> > +static void write_regs(QTestState *s, uint32_t base, uint64_t src,
> > +                       uint32_t length, uint64_t out, uint32_t
> > +method)
> >   {
> > -        qtest_writel(s, base + HACE_HASH_SRC, src);
> > -        qtest_writel(s, base + HACE_HASH_DIGEST, out);
> > +        qtest_writel(s, base + HACE_HASH_SRC, extract64(src, 0, 32));
> > +        qtest_writel(s, base + HACE_HASH_DIGEST, extract64(out, 0,
> > + 32));
> >           qtest_writel(s, base + HACE_HASH_DATA_LEN, length);
> >           qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN |
> method);
> >   }
> >
> >   void aspeed_test_md5(const char *machine, const uint32_t base,
> > -                     const uint32_t src_addr)
> > +                     const uint64_t src_addr)
> >
> >   {
> >       QTestState *s = qtest_init(machine);
> >
> > -    uint32_t digest_addr = src_addr + 0x010000;
> > +    uint64_t digest_addr = src_addr + 0x010000;
> >       uint8_t digest[16] = {0};
> >
> >       /* Check engine is idle, no busy or irq bits set */ @@ -198,11
> > +198,11 @@ void aspeed_test_md5(const char *machine, const uint32_t
> base,
> >   }
> >
> >   void aspeed_test_sha256(const char *machine, const uint32_t base,
> > -                        const uint32_t src_addr)
> > +                        const uint64_t src_addr)
> >   {
> >       QTestState *s = qtest_init(machine);
> >
> > -    const uint32_t digest_addr = src_addr + 0x10000;
> > +    const uint64_t digest_addr = src_addr + 0x10000;
> >       uint8_t digest[32] = {0};
> >
> >       /* Check engine is idle, no busy or irq bits set */ @@ -232,11
> > +232,11 @@ void aspeed_test_sha256(const char *machine, const uint32_t
> base,
> >   }
> >
> >   void aspeed_test_sha384(const char *machine, const uint32_t base,
> > -                        const uint32_t src_addr)
> > +                        const uint64_t src_addr)
> >   {
> >       QTestState *s = qtest_init(machine);
> >
> > -    const uint32_t digest_addr = src_addr + 0x10000;
> > +    const uint64_t digest_addr = src_addr + 0x10000;
> >       uint8_t digest[32] = {0};
> >
> >       /* Check engine is idle, no busy or irq bits set */ @@ -266,11
> > +266,11 @@ void aspeed_test_sha384(const char *machine, const uint32_t
> base,
> >   }
> >
> >   void aspeed_test_sha512(const char *machine, const uint32_t base,
> > -                        const uint32_t src_addr)
> > +                        const uint64_t src_addr)
> >   {
> >       QTestState *s = qtest_init(machine);
> >
> > -    const uint32_t digest_addr = src_addr + 0x10000;
> > +    const uint64_t digest_addr = src_addr + 0x10000;
> >       uint8_t digest[64] = {0};
> >
> >       /* Check engine is idle, no busy or irq bits set */ @@ -300,22
> > +300,22 @@ void aspeed_test_sha512(const char *machine, const uint32_t
> base,
> >   }
> >
> >   void aspeed_test_sha256_sg(const char *machine, const uint32_t base,
> > -                           const uint32_t src_addr)
> > +                           const uint64_t src_addr)
> >   {
> >       QTestState *s = qtest_init(machine);
> >
> > -    const uint32_t src_addr_1 = src_addr + 0x10000;
> > -    const uint32_t src_addr_2 = src_addr + 0x20000;
> > -    const uint32_t src_addr_3 = src_addr + 0x30000;
> > -    const uint32_t digest_addr = src_addr + 0x40000;
> > +    const uint64_t src_addr_1 = src_addr + 0x10000;
> > +    const uint64_t src_addr_2 = src_addr + 0x20000;
> > +    const uint64_t src_addr_3 = src_addr + 0x30000;
> > +    const uint64_t digest_addr = src_addr + 0x40000;
> >       uint8_t digest[32] = {0};
> >       struct AspeedSgList array[] = {
> >           {  cpu_to_le32(sizeof(test_vector_sg1)),
> > -           cpu_to_le32(src_addr_1) },
> > +           cpu_to_le64(src_addr_1) },
> 
> 
> This looks broken to me. The addr field is in the scatter-gather list entry is
> 32bit :
> 
>    struct AspeedSgList {
>            uint32_t len;
>            uint32_t addr;
>    } __attribute__ ((__packed__));
> 
> 
Thanks for the review.
Will fix it.
Jamin
> 
> Thanks,
> 
> C.
> 
> 
> >           {  cpu_to_le32(sizeof(test_vector_sg2)),
> > -           cpu_to_le32(src_addr_2) },
> > +           cpu_to_le64(src_addr_2) },
> >           {  cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST),
> > -           cpu_to_le32(src_addr_3) },
> > +           cpu_to_le64(src_addr_3) },
> >       };
> >
> >       /* Check engine is idle, no busy or irq bits set */ @@ -351,22
> > +351,22 @@ void aspeed_test_sha256_sg(const char *machine, const
> uint32_t base,
> >   }
> >
> >   void aspeed_test_sha384_sg(const char *machine, const uint32_t base,
> > -                           const uint32_t src_addr)
> > +                           const uint64_t src_addr)
> >   {
> >       QTestState *s = qtest_init(machine);
> >
> > -    const uint32_t src_addr_1 = src_addr + 0x10000;
> > -    const uint32_t src_addr_2 = src_addr + 0x20000;
> > -    const uint32_t src_addr_3 = src_addr + 0x30000;
> > -    const uint32_t digest_addr = src_addr + 0x40000;
> > +    const uint64_t src_addr_1 = src_addr + 0x10000;
> > +    const uint64_t src_addr_2 = src_addr + 0x20000;
> > +    const uint64_t src_addr_3 = src_addr + 0x30000;
> > +    const uint64_t digest_addr = src_addr + 0x40000;
> >       uint8_t digest[64] = {0};
> >       struct AspeedSgList array[] = {
> >           {  cpu_to_le32(sizeof(test_vector_sg1)),
> > -           cpu_to_le32(src_addr_1) },
> > +           cpu_to_le64(src_addr_1) },
> >           {  cpu_to_le32(sizeof(test_vector_sg2)),
> > -           cpu_to_le32(src_addr_2) },
> > +           cpu_to_le64(src_addr_2) },
> >           {  cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST),
> > -           cpu_to_le32(src_addr_3) },
> > +           cpu_to_le64(src_addr_3) },
> >       };
> >
> >       /* Check engine is idle, no busy or irq bits set */ @@ -402,22
> > +402,22 @@ void aspeed_test_sha384_sg(const char *machine, const
> uint32_t base,
> >   }
> >
> >   void aspeed_test_sha512_sg(const char *machine, const uint32_t base,
> > -                           const uint32_t src_addr)
> > +                           const uint64_t src_addr)
> >   {
> >       QTestState *s = qtest_init(machine);
> >
> > -    const uint32_t src_addr_1 = src_addr + 0x10000;
> > -    const uint32_t src_addr_2 = src_addr + 0x20000;
> > -    const uint32_t src_addr_3 = src_addr + 0x30000;
> > -    const uint32_t digest_addr = src_addr + 0x40000;
> > +    const uint64_t src_addr_1 = src_addr + 0x10000;
> > +    const uint64_t src_addr_2 = src_addr + 0x20000;
> > +    const uint64_t src_addr_3 = src_addr + 0x30000;
> > +    const uint64_t digest_addr = src_addr + 0x40000;
> >       uint8_t digest[64] = {0};
> >       struct AspeedSgList array[] = {
> >           {  cpu_to_le32(sizeof(test_vector_sg1)),
> > -           cpu_to_le32(src_addr_1) },
> > +           cpu_to_le64(src_addr_1) },
> >           {  cpu_to_le32(sizeof(test_vector_sg2)),
> > -           cpu_to_le32(src_addr_2) },
> > +           cpu_to_le64(src_addr_2) },
> >           {  cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST),
> > -           cpu_to_le32(src_addr_3) },
> > +           cpu_to_le64(src_addr_3) },
> >       };
> >
> >       /* Check engine is idle, no busy or irq bits set */ @@ -453,16
> > +453,16 @@ void aspeed_test_sha512_sg(const char *machine, const
> uint32_t base,
> >   }
> >
> >   void aspeed_test_sha256_accum(const char *machine, const uint32_t
> base,
> > -                              const uint32_t src_addr)
> > +                              const uint64_t src_addr)
> >   {
> >       QTestState *s = qtest_init(machine);
> >
> > -    const uint32_t buffer_addr = src_addr + 0x10000;
> > -    const uint32_t digest_addr = src_addr + 0x40000;
> > +    const uint64_t buffer_addr = src_addr + 0x10000;
> > +    const uint64_t digest_addr = src_addr + 0x40000;
> >       uint8_t digest[32] = {0};
> >       struct AspeedSgList array[] = {
> >           {  cpu_to_le32(sizeof(test_vector_accum_256) |
> SG_LIST_LEN_LAST),
> > -           cpu_to_le32(buffer_addr) },
> > +           cpu_to_le64(buffer_addr) },
> >       };
> >
> >       /* Check engine is idle, no busy or irq bits set */ @@ -494,16
> > +494,16 @@ void aspeed_test_sha256_accum(const char *machine, const
> uint32_t base,
> >   }
> >
> >   void aspeed_test_sha384_accum(const char *machine, const uint32_t
> base,
> > -                              const uint32_t src_addr)
> > +                              const uint64_t src_addr)
> >   {
> >       QTestState *s = qtest_init(machine);
> >
> > -    const uint32_t buffer_addr = src_addr + 0x10000;
> > -    const uint32_t digest_addr = src_addr + 0x40000;
> > +    const uint64_t buffer_addr = src_addr + 0x10000;
> > +    const uint64_t digest_addr = src_addr + 0x40000;
> >       uint8_t digest[64] = {0};
> >       struct AspeedSgList array[] = {
> >           {  cpu_to_le32(sizeof(test_vector_accum_384) |
> SG_LIST_LEN_LAST),
> > -           cpu_to_le32(buffer_addr) },
> > +           cpu_to_le64(buffer_addr) },
> >       };
> >
> >       /* Check engine is idle, no busy or irq bits set */ @@ -535,16
> > +535,16 @@ void aspeed_test_sha384_accum(const char *machine, const
> uint32_t base,
> >   }
> >
> >   void aspeed_test_sha512_accum(const char *machine, const uint32_t
> base,
> > -                              const uint32_t src_addr)
> > +                              const uint64_t src_addr)
> >   {
> >       QTestState *s = qtest_init(machine);
> >
> > -    const uint32_t buffer_addr = src_addr + 0x10000;
> > -    const uint32_t digest_addr = src_addr + 0x40000;
> > +    const uint64_t buffer_addr = src_addr + 0x10000;
> > +    const uint64_t digest_addr = src_addr + 0x40000;
> >       uint8_t digest[64] = {0};
> >       struct AspeedSgList array[] = {
> >           {  cpu_to_le32(sizeof(test_vector_accum_512) |
> SG_LIST_LEN_LAST),
> > -           cpu_to_le32(buffer_addr) },
> > +           cpu_to_le64(buffer_addr) },
> >       };
> >
> >       /* Check engine is idle, no busy or irq bits set */