Re: [PATCH 14/50] ppc/xive: Explicitly zero NSR after accepting

[Miles Glenn]

Reviewed-by: Glenn Miles <milesg@linux.ibm.com>

On Mon, 2025-05-12 at 13:10 +1000, Nicholas Piggin wrote:
> Have xive_tctx_accept clear NSR in one shot rather than masking out bits
> as they are tested, which makes it clear it's reset to 0, and does not
> have a partial NSR value in the register.
> 
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
>  hw/intc/xive.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index 6293ea4361..bb40a69c5b 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -68,13 +68,11 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t 
> ring)
>           * If the interrupt was for a specific VP, reset the pending
>           * buffer bit, otherwise clear the logical server indicator
>           */
> -        if (regs[TM_NSR] & TM_NSR_GRP_LVL) {
> -            regs[TM_NSR] &= ~TM_NSR_GRP_LVL;
> -        } else {
> +        if (!(regs[TM_NSR] & TM_NSR_GRP_LVL)) {
>              alt_regs[TM_IPB] &= ~xive_priority_to_ipb(cppr);
>          }
>  
> -        /* Drop the exception bit and any group/crowd */
> +        /* Clear the exception from NSR */
>          regs[TM_NSR] = 0;
>  
>          trace_xive_tctx_accept(tctx->cs->cpu_index, alt_ring,