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Re: [Qemu-ppc] [PATCH 1/3] spapr pci msi: rework
From: |
Anthony Liguori |
Subject: |
Re: [Qemu-ppc] [PATCH 1/3] spapr pci msi: rework |
Date: |
Fri, 21 Jun 2013 06:58:49 -0500 |
User-agent: |
Notmuch/0.15.2+77~g661dcf8 (http://notmuchmail.org) Emacs/23.3.1 (x86_64-pc-linux-gnu) |
Alexey Kardashevskiy <address@hidden> writes:
> On 06/21/2013 08:31 PM, Alexander Graf wrote:
>>
>> On 21.06.2013, at 11:22, Alexey Kardashevskiy wrote:
>>
>>> Previously every PCI host bridge implemented its own MSI memory window
>>> in order to catch msi_notify()/msix_notify() calls from various QEMU
>>> MSI-capable devives such as virtio-pci or vfio and redirect them to
>>> the guest via qemu_pulse_irq().
>>
>> That's how hardware works, no?
>>
>>>
>>> The encoded MSIMessage used to be encoded as:
>>> * .addr - address in a MSI window, this is how QEMU knows which PHB
>>> is the message for;
>>> * .data - number of a device on a specific PHB and vector number.
>>>
>>> As a PHB has a destriptor for every device, and every descriptor has
>>> first IRQ number and the number of IRQs, it can calculate global IRQ
>>> number to use in qemu_pulse_irq().
>>
>> How does this work on real hardware?
>
>
> I do not understand the question, really. Here we are emulating pHyp which
> is not real hardware and never pretended to be. Our guests do not touch MSI
> records in the config space and use RTAS MSI calls instead.
But RTAS is implemented as guest code. I suspect it's doing region
access to generate the actual MSI events.
Regards,
Anthony Liguori
>
>
>>
>>
>> Alex
>>
>>> However the total number of IRQs is not really big (at the moment it is
>>> 1024 IRQs which start from 4096) and the existing system looks overdesigned.
>>> The patch simplifies it. Specifically:
>>>
>>> 1. MSI windows were removed from PHB.
>>> 2. Added one memory region for all MSIs.
>>> 3. Now MSIMessage::addr is a number of first IRQ of a device,
>>> MSIMessage:data is a number of a vector.
>>>
>>> Putting IRQ number to .data and not using .addr would make it even simpler
>>> for MSI-X but it will not work for MSI with multiple vectors unless a first
>>> IRQ number of a device is aligned to the MSI vectors number.
>>>
>>> The simplified scheme also allows easier MSIMessage->IRQ translation
>>> for upcoming IRQFD support.
>>>
>>> Signed-off-by: Alexey Kardashevskiy <address@hidden>
>>
>
>
> --
> Alexey
[Qemu-ppc] [PATCH 2/3] KVM: add kvm_arch_irqchip_add_msi_route, Alexey Kardashevskiy, 2013/06/21
- Re: [Qemu-ppc] [PATCH 2/3] KVM: add kvm_arch_irqchip_add_msi_route, Alexander Graf, 2013/06/21
- Re: [Qemu-ppc] [PATCH 2/3] KVM: add kvm_arch_irqchip_add_msi_route, Benjamin Herrenschmidt, 2013/06/21
- Re: [Qemu-ppc] [PATCH 2/3] KVM: add kvm_arch_irqchip_add_msi_route, Alexander Graf, 2013/06/21
- Re: [Qemu-ppc] [PATCH 2/3] KVM: add kvm_arch_irqchip_add_msi_route, Benjamin Herrenschmidt, 2013/06/21
- Re: [Qemu-ppc] [PATCH 2/3] KVM: add kvm_arch_irqchip_add_msi_route, Alexander Graf, 2013/06/21
- Re: [Qemu-ppc] [PATCH 2/3] KVM: add kvm_arch_irqchip_add_msi_route, Benjamin Herrenschmidt, 2013/06/21