[Qemu-ppc] [PATCH] target-ppc: Little Endian Correction to Load/Store Vector Element

[Anton Blanchard]

From: Tom Musta <address@hidden>

The Load Vector Element (lve*x) and Store Vector Element (stve*x)
instructions not only byte-swap in Little Endian mode, they also
invert the element that is accessed. For example, the RTL for
lvehx contains this:

     eb <-- EA[60:63]
     if Big-Endian byte ordering then
         VRT[8*eb:8*eb+15] <-- MEM(EA,2)
     else
         VRT[112-(8*eb):127-(8*eb)] <-- MEM(EA,2)

This patch adds the element inversion, as described in the last line
of the RTL.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Anton Blanchard <address@hidden>
---

Index: b/target-ppc/mem_helper.c
===================================================================
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -212,6 +212,7 @@ target_ulong helper_lscbx(CPUPPCState *e
         int index = (addr & 0xf) >> sh;                         \
                                                                 \
         if (msr_le) {                                           \
+            index = n_elems - index - 1;                        \
             r->element[LO_IDX ? index : (adjust - index)] =     \
                 swap(access(env, addr));                        \
         } else {                                                \
@@ -236,6 +237,7 @@ LVE(lvewx, cpu_ldl_data, bswap32, u32)
         int index = (addr & 0xf) >> sh;                                 \
                                                                         \
         if (msr_le) {                                                   \
+            index = n_elems - index - 1;                                \
             access(env, addr, swap(r->element[LO_IDX ? index :          \
                                               (adjust - index)]));      \
         } else {                                                        \