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[Qemu-ppc] [V6 PATCH 03/18] target-ppc: VSX Stage 4: Add lxsiwax, lxsiwz
From: |
Tom Musta |
Subject: |
[Qemu-ppc] [V6 PATCH 03/18] target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx |
Date: |
Fri, 10 Jan 2014 13:07:47 -0600 |
This patch adds the scalar load instructions introduced in ISA
V2.07:
- Load VSX Scalar as Integer Word Algebraic Indexd (lxsiwax)
- Load VSX Scalar as Integer Word and Zero Indexed (lxsiwzx)
- Load VSX Scalar Single-Precision Indexed (lxsspx)
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
V5: Updated to fix tcg-debug compilation failures.
target-ppc/translate.c | 14 ++++++++++++++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index ca26dcf..958ea94 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2585,6 +2585,14 @@ static inline void gen_qemu_ld32s(DisasContext *ctx,
TCGv arg1, TCGv arg2)
tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
}
+static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
+{
+ TCGv tmp = tcg_temp_new();
+ gen_qemu_ld32s(ctx, tmp, addr);
+ tcg_gen_ext_tl_i64(val, tmp);
+ tcg_temp_free(tmp);
+}
+
static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
{
tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
@@ -7039,6 +7047,9 @@ static void gen_##name(DisasContext *ctx)
\
}
VSX_LOAD_SCALAR(lxsdx, ld64)
+VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
+VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
+VSX_LOAD_SCALAR(lxsspx, ld32fs)
static void gen_lxvd2x(DisasContext *ctx)
{
@@ -10044,6 +10055,9 @@ GEN_VAFORM_PAIRED(vsel, vperm, 21),
GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
+GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
--
1.7.1
- [Qemu-ppc] [V6 PATCH 00/18] target-ppc: VSX Stage 4, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 01/18] target-ppc: VSX Stage 4: Add VSX 2.07 Flag, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 02/18] target-ppc: VSX Stage 4: Refactor lxsdx, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 03/18] target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx,
Tom Musta <=
- [Qemu-ppc] [V6 PATCH 04/18] target-ppc: VSX Stage 4: Refactor stxsdx, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 05/18] target-ppc: VSX Stage 4: Add stxsiwx and stxsspx, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 06/18] target-ppc: VSX Stage 4: Add xsaddsp and xssubsp, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 07/18] target-ppc: VSX Stage 4: Add xsmulsp, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 08/18] target-ppc: VSX Stage 4: Add xsdivsp, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 09/18] target-ppc: VSX Stage 4: Add xsresp, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 13/18] target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 14/18] target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 12/18] target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds, Tom Musta, 2014/01/10
- [Qemu-ppc] [V6 PATCH 15/18] target-ppc: Move To/From VSR Instructions, Tom Musta, 2014/01/10