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[Qemu-ppc] [PULL 100/130] target-ppc: Altivec 2.07: Multiply Even/Odd Wo
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PULL 100/130] target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions |
Date: |
Fri, 7 Mar 2014 00:33:47 +0100 |
From: Tom Musta <address@hidden>
This patch adds the Multilpy Even/Odd Word instructions that are introduced
in Power ISA Version 2.07:
- Vector Multiply Even Unsigned Word (vmuleuw)
- Vector Multiply Even Signed Word (vmulesw)
- Vector Multiply Odd Unsigned Word (vmulouw)
- Vector Multiply Odd Signed Word (vmulosw)
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/helper.h | 4 ++++
target-ppc/int_helper.c | 2 ++
target-ppc/translate.c | 8 ++++++++
3 files changed, 14 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 1106e29..ca18447 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -166,12 +166,16 @@ DEF_HELPER_3(vmrghh, void, avr, avr, avr)
DEF_HELPER_3(vmrghw, void, avr, avr, avr)
DEF_HELPER_3(vmulesb, void, avr, avr, avr)
DEF_HELPER_3(vmulesh, void, avr, avr, avr)
+DEF_HELPER_3(vmulesw, void, avr, avr, avr)
DEF_HELPER_3(vmuleub, void, avr, avr, avr)
DEF_HELPER_3(vmuleuh, void, avr, avr, avr)
+DEF_HELPER_3(vmuleuw, void, avr, avr, avr)
DEF_HELPER_3(vmulosb, void, avr, avr, avr)
DEF_HELPER_3(vmulosh, void, avr, avr, avr)
+DEF_HELPER_3(vmulosw, void, avr, avr, avr)
DEF_HELPER_3(vmuloub, void, avr, avr, avr)
DEF_HELPER_3(vmulouh, void, avr, avr, avr)
+DEF_HELPER_3(vmulouw, void, avr, avr, avr)
DEF_HELPER_3(vsrab, void, avr, avr, avr)
DEF_HELPER_3(vsrah, void, avr, avr, avr)
DEF_HELPER_3(vsraw, void, avr, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 20d34e6..09590c7 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1005,8 +1005,10 @@ void helper_vmsumuhs(CPUPPCState *env, ppc_avr_t *r,
ppc_avr_t *a,
VMUL_DO(mulo##suffix, mul_element, prod_element, cast, 0)
VMUL(sb, s8, s16, int16_t)
VMUL(sh, s16, s32, int32_t)
+VMUL(sw, s32, s64, int64_t)
VMUL(ub, u8, u16, uint16_t)
VMUL(uh, u16, u32, uint32_t)
+VMUL(uw, u32, u64, uint64_t)
#undef VMUL_DO
#undef VMUL
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index b1986f4..4d2579d 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6963,12 +6963,16 @@ GEN_VXFORM(vmrglh, 6, 5);
GEN_VXFORM(vmrglw, 6, 6);
GEN_VXFORM(vmuloub, 4, 0);
GEN_VXFORM(vmulouh, 4, 1);
+GEN_VXFORM(vmulouw, 4, 2);
GEN_VXFORM(vmulosb, 4, 4);
GEN_VXFORM(vmulosh, 4, 5);
+GEN_VXFORM(vmulosw, 4, 6);
GEN_VXFORM(vmuleub, 4, 8);
GEN_VXFORM(vmuleuh, 4, 9);
+GEN_VXFORM(vmuleuw, 4, 10);
GEN_VXFORM(vmulesb, 4, 12);
GEN_VXFORM(vmulesh, 4, 13);
+GEN_VXFORM(vmulesw, 4, 14);
GEN_VXFORM(vslb, 2, 4);
GEN_VXFORM(vslh, 2, 5);
GEN_VXFORM(vslw, 2, 6);
@@ -10371,12 +10375,16 @@ GEN_VXFORM(vmrglh, 6, 5),
GEN_VXFORM(vmrglw, 6, 6),
GEN_VXFORM(vmuloub, 4, 0),
GEN_VXFORM(vmulouh, 4, 1),
+GEN_VXFORM_207(vmulouw, 4, 2),
GEN_VXFORM(vmulosb, 4, 4),
GEN_VXFORM(vmulosh, 4, 5),
+GEN_VXFORM_207(vmulosw, 4, 6),
GEN_VXFORM(vmuleub, 4, 8),
GEN_VXFORM(vmuleuh, 4, 9),
+GEN_VXFORM_207(vmuleuw, 4, 10),
GEN_VXFORM(vmulesb, 4, 12),
GEN_VXFORM(vmulesh, 4, 13),
+GEN_VXFORM_207(vmulesw, 4, 14),
GEN_VXFORM(vslb, 2, 4),
GEN_VXFORM(vslh, 2, 5),
GEN_VXFORM(vslw, 2, 6),
--
1.8.1.4
- [Qemu-ppc] [PULL 088/130] target-ppc: Store Quadword, (continued)
- [Qemu-ppc] [PULL 088/130] target-ppc: Store Quadword, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 090/130] target-ppc: Add Store Quadword Conditional, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 073/130] Add Enhanced Three-Speed Ethernet Controller (eTSEC), Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 092/130] target-ppc: Altivec 2.07: Update AVR Structure, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 097/130] target-ppc: Altivec 2.07: Vector Logical Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 095/130] target-ppc: Altivec 2.07: Add Opcode Macro for VX Form Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 094/130] target-ppc: Altivec 2.07: Add Support for Dual Altivec Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 096/130] target-ppc: Altivec 2.07: Add Support for R-Form Dual Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 093/130] target-ppc: Altivec 2.07: Add GEN_VXFORM3, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 104/130] target-ppc: Altivec 2.07: Vector Min/Max Doubleword Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 100/130] target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions,
Alexander Graf <=
- [Qemu-ppc] [PULL 101/130] target-ppc: Altivec 2.07: vmuluw Instruction, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 102/130] target-ppc: Altivec 2.07: Add Vector Count Leading Zeroes, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 120/130] target-ppc/translate.c: Use ULL suffix for 64 bit constants, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 106/130] target-ppc: Altivec 2.07: Unpack Signed Word Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 109/130] target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 108/130] target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates and Shifts, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 103/130] target-ppc: Altivec 2.07: Vector Population Count Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 098/130] target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword Modulo, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 107/130] target-ppc: Altivec 2.07: Vector Merge Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 110/130] target-ppc: Altivec 2.07: Quadword Addition and Subtracation, Alexander Graf, 2014/03/06