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[Qemu-ppc] [PULL 051/130] target-ppc: Scalar Non-Signalling Conversions
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PULL 051/130] target-ppc: Scalar Non-Signalling Conversions |
Date: |
Fri, 7 Mar 2014 00:32:58 +0100 |
From: Tom Musta <address@hidden>
This patch adds the non-signalling scalar conversion instructions:
- VSX Scalar Convert Single Precision to Double Precision
Non-Signalling (xscvspdpn)
- VSX Scalar Convert Double Precision to Single Precision
Non-Signalling (xscvdpspn)
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/fpu_helper.c | 16 ++++++++++++++++
target-ppc/helper.h | 2 ++
target-ppc/translate.c | 4 ++++
3 files changed, 22 insertions(+)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index c35135e..dfd9b80 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2487,6 +2487,22 @@ VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, f32[j],
f64[i], 1)
VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, f64[i], f32[j], 0)
VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, f32[j], f64[i], 0)
+uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
+{
+ float_status tstat = env->fp_status;
+ set_float_exception_flags(0, &tstat);
+
+ return (uint64_t)float64_to_float32(xb, &tstat) << 32;
+}
+
+uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t xb)
+{
+ float_status tstat = env->fp_status;
+ set_float_exception_flags(0, &tstat);
+
+ return float32_to_float64(xb >> 32, &tstat);
+}
+
/* VSX_CVT_FP_TO_INT - VSX floating point to integer conversion
* op - instruction mnemonic
* nels - number of elements (1, 2 or 4)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 1654589..0976930 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -273,7 +273,9 @@ DEF_HELPER_2(xscmpudp, void, env, i32)
DEF_HELPER_2(xsmaxdp, void, env, i32)
DEF_HELPER_2(xsmindp, void, env, i32)
DEF_HELPER_2(xscvdpsp, void, env, i32)
+DEF_HELPER_2(xscvdpspn, i64, env, i64)
DEF_HELPER_2(xscvspdp, void, env, i32)
+DEF_HELPER_2(xscvspdpn, i64, env, i64)
DEF_HELPER_2(xscvdpsxds, void, env, i32)
DEF_HELPER_2(xscvdpsxws, void, env, i32)
DEF_HELPER_2(xscvdpuxds, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index c307f24..d57d683 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7437,7 +7437,9 @@ GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
+GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
+GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
@@ -10275,7 +10277,9 @@ GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
+GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
+GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
--
1.8.1.4
- [Qemu-ppc] [PULL 032/130] target-ppc: Add VSX ISA2.06 Integer Conversion Instructions, (continued)
- [Qemu-ppc] [PULL 032/130] target-ppc: Add VSX ISA2.06 Integer Conversion Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 048/130] target-ppc: Move To/From VSR Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 055/130] target-ppc: Add ISA2.06 divde[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 053/130] target-ppc: Add Flag for ISA2.06 Divide Extended Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 052/130] target-ppc: Add ISA2.06 bpermd Instruction, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 068/130] target-ppc: Enable frsqrtes on Power7 and Power8, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 069/130] target-ppc: Add ISA2.06 lfiwzx Instruction, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 054/130] target-ppc: Add ISA2.06 divdeu[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 067/130] target-ppc: Add ISA 2.06 ftsqrt, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 061/130] target-ppc: Add Flag for ISA V2.06 Floating Point Conversion, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 051/130] target-ppc: Scalar Non-Signalling Conversions,
Alexander Graf <=
- [Qemu-ppc] [PULL 071/130] virtex_ml507: Add support for loading initrd images, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 060/130] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 070/130] PPC: KVM: store SLB slot number, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 065/130] target-ppc: Add Flag for Power ISA V2.06 Floating Point Test Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 062/130] target-ppc: Add ISA2.06 Float to Integer Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 074/130] spapr: support only ELF kernel images, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 066/130] target-ppc: Add ISA 2.06 ftdiv Instruction, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 063/130] target-ppc: Add ISA 2.06 fcfid[u][s] Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 072/130] PPC: KVM: suppress warnings about not supported SPRs, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 059/130] target-ppc: Add ISA2.06 lbarx, lharx Instructions, Alexander Graf, 2014/03/06