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[Qemu-ppc] [PULL 058/130] target-ppc: Add Flag for ISA2.06 Atomic Instru
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PULL 058/130] target-ppc: Add Flag for ISA2.06 Atomic Instructions |
Date: |
Fri, 7 Mar 2014 00:33:05 +0100 |
From: Tom Musta <address@hidden>
This patch adds a flag for the atomic instructions introduced
in Power ISA V2.06B.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/cpu.h | 5 ++++-
target-ppc/translate_init.c | 9 ++++++---
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index ab900a4..bf2b64f 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1881,10 +1881,13 @@ enum {
PPC2_PERM_ISA206 = 0x0000000000000080ULL,
/* ISA 2.06B divide extended variants */
PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
+ /* ISA 2.06B larx/stcx. instructions */
+ PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
+
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
- PPC2_DIVE_ISA206)
+ PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206)
};
/*****************************************************************************/
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 76f326d..abe0a21 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7069,7 +7069,8 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
- PPC2_PERM_ISA206 | PPC2_DIVE_ISA206;
+ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
+ PPC2_ATOMIC_ISA206;
pcc->msr_mask = 0x800000000284FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
@@ -7108,7 +7109,8 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
- PPC2_PERM_ISA206 | PPC2_DIVE_ISA206;
+ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
+ PPC2_ATOMIC_ISA206;
pcc->msr_mask = 0x800000000204FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
@@ -7147,7 +7149,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD;
pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
- PPC2_PERM_ISA206 | PPC2_DIVE_ISA206;
+ PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
+ PPC2_ATOMIC_ISA206;
pcc->msr_mask = 0x800000000284FF36ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
--
1.8.1.4
- [Qemu-ppc] [PULL 126/130] target-ppc: Change the hpte store API, (continued)
- [Qemu-ppc] [PULL 126/130] target-ppc: Change the hpte store API, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 127/130] target-ppc: Update ppc_hash64_store_hpte to support updating in-kernel htab, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 128/130] target-ppc: Introduce hypervisor call H_GET_TCE, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 122/130] target-ppc: Fix Compiler Warnings Due to 64-Bit Constants Declared as UL, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 040/130] target-ppc: VSX Stage 4: Add xsmulsp, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 028/130] target-ppc: Add VSX xscmp*dp Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 035/130] target-ppc: VSX Stage 4: Refactor lxsdx, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 025/130] target-ppc: Add VSX ISA2.06 xtdiv Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 044/130] target-ppc: VSX Stage 4: add xsrsqrtesp, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 050/130] target-ppc: Scalar Round to Single Precision, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 058/130] target-ppc: Add Flag for ISA2.06 Atomic Instructions,
Alexander Graf <=
- [Qemu-ppc] [PULL 045/130] target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 030/130] target-ppc: Add VSX Vector Compare Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 026/130] target-ppc: Add VSX ISA2.06 xtsqrt Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 018/130] target-ppc: General Support for VSX Helpers, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 112/130] target-ppc: Altivec 2.07: Doubleword Compares, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 042/130] target-ppc: VSX Stage 4: Add xsresp, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 046/130] target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 039/130] target-ppc: VSX Stage 4: Add xsaddsp and xssubsp, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 057/130] target-ppc: Add ISA 2.06 divwe[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-ppc] [PULL 033/130] target-ppc: Add VSX Rounding Instructions, Alexander Graf, 2014/03/06