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[Qemu-ppc] [PATCH v2] target-ppc: improve "info registers" by printing S
From: |
Alexey Kardashevskiy |
Subject: |
[Qemu-ppc] [PATCH v2] target-ppc: improve "info registers" by printing SPRs |
Date: |
Sat, 22 Mar 2014 23:25:49 +1100 |
This adds printing of all SPR registers registered for a CPU.
This removes "SPR_" prefix from SPR name to reduce the output.
Cc: Fabien Chouteau <address@hidden>
Signed-off-by: Alexey Kardashevskiy <address@hidden>
---
Changes:
v2:
* removed "switch (env->mmu_model)"
* added "\n" if the last line has less than 4 registers
---
target-ppc/translate.c | 96 +++++++--------------------------------------
target-ppc/translate_init.c | 40 +++++++++----------
2 files changed, 35 insertions(+), 101 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e3fcb03..06f195a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -11116,7 +11116,7 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf,
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
- int i;
+ int i, j;
cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
@@ -11167,54 +11167,22 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf,
cpu_fprintf(f, "\n");
}
cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
-#if !defined(CONFIG_USER_ONLY)
- cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
- " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
- env->spr[SPR_SRR0], env->spr[SPR_SRR1],
- env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
- cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
- " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
- env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
- env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
-
- cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
- " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
- env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
- env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
-
- if (env->excp_model == POWERPC_EXCP_BOOKE) {
- cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
- " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
- env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
- env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
-
- cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
- " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
- env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
- env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
-
- cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
- " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
- env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
- env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
-
- cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
- " EPR " TARGET_FMT_lx "\n",
- env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
- env->spr[SPR_BOOKE_EPR]);
-
- /* FSL-specific */
- cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
- " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
- env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
- env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
-
- /*
- * IVORs are left out as they are large and do not change often --
- * they can be read with "p $ivor0", "p $ivor1", etc.
- */
+ for (i = 0, j = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
+ ppc_spr_t *spr = &env->spr_cb[i];
+
+ if (!spr->name) {
+ continue;
+ }
+ cpu_fprintf(f, "%-6s " TARGET_FMT_lx, spr->name, env->spr[i]);
+ j++;
+ if (!(j % 4) || (i == ARRAY_SIZE(env->spr_cb) - 1)) {
+ cpu_fprintf(f, "\n");
+ } else {
+ cpu_fprintf(f, " ");
+ }
}
+#if !defined(CONFIG_USER_ONLY)
#if defined(TARGET_PPC64)
if (env->flags & POWERPC_FLAG_CFAR) {
@@ -11222,40 +11190,6 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf,
}
#endif
- switch (env->mmu_model) {
- case POWERPC_MMU_32B:
- case POWERPC_MMU_601:
- case POWERPC_MMU_SOFT_6xx:
- case POWERPC_MMU_SOFT_74xx:
-#if defined(TARGET_PPC64)
- case POWERPC_MMU_64B:
- case POWERPC_MMU_2_06:
- case POWERPC_MMU_2_06a:
- case POWERPC_MMU_2_06d:
-#endif
- cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
- " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
- env->spr[SPR_DAR], env->spr[SPR_DSISR]);
- break;
- case POWERPC_MMU_BOOKE206:
- cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
- " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
- env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
- env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
-
- cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
- " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
- env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
- env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
-
- cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
- " TLB1CFG " TARGET_FMT_lx "\n",
- env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
- env->spr[SPR_BOOKE_TLB1CFG]);
- break;
- default:
- break;
- }
#endif
#undef RGPL
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 954dee3..4d199c1 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -3834,7 +3834,7 @@ static void init_proc_460 (CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
+ spr_register(env, SPR_DCRIPR, "DCRIPR",
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic,
0x00000000);
@@ -3930,7 +3930,7 @@ static void init_proc_460F (CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* XXX : not implemented */
- spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
+ spr_register(env, SPR_DCRIPR, "DCRIPR",
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic,
0x00000000);
@@ -6654,7 +6654,7 @@ static void init_proc_970 (CPUPPCState *env)
/* Memory management */
/* XXX: not correct */
gen_low_BATs(env);
- spr_register(env, SPR_HIOR, "SPR_HIOR",
+ spr_register(env, SPR_HIOR, "HIOR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_hior, &spr_write_hior,
0x00000000);
@@ -6734,19 +6734,19 @@ static void init_proc_970FX (CPUPPCState *env)
/* Memory management */
/* XXX: not correct */
gen_low_BATs(env);
- spr_register(env, SPR_HIOR, "SPR_HIOR",
+ spr_register(env, SPR_HIOR, "HIOR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_hior, &spr_write_hior,
0x00000000);
- spr_register(env, SPR_CTRL, "SPR_CTRL",
+ spr_register(env, SPR_CTRL, "CTRL",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, &spr_write_generic,
0x00000000);
- spr_register(env, SPR_UCTRL, "SPR_UCTRL",
+ spr_register(env, SPR_UCTRL, "UCTRL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
- spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
+ spr_register(env, SPR_VRSAVE, "VRSAVE",
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic,
0x00000000);
@@ -6827,7 +6827,7 @@ static void init_proc_970MP (CPUPPCState *env)
/* Memory management */
/* XXX: not correct */
gen_low_BATs(env);
- spr_register(env, SPR_HIOR, "SPR_HIOR",
+ spr_register(env, SPR_HIOR, "HIOR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_hior, &spr_write_hior,
0x00000000);
@@ -6904,19 +6904,19 @@ static void init_proc_power5plus(CPUPPCState *env)
/* Memory management */
/* XXX: not correct */
gen_low_BATs(env);
- spr_register(env, SPR_HIOR, "SPR_HIOR",
+ spr_register(env, SPR_HIOR, "HIOR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_hior, &spr_write_hior,
0x00000000);
- spr_register(env, SPR_CTRL, "SPR_CTRL",
+ spr_register(env, SPR_CTRL, "CTRL",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, &spr_write_generic,
0x00000000);
- spr_register(env, SPR_UCTRL, "SPR_UCTRL",
+ spr_register(env, SPR_UCTRL, "UCTRL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
- spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
+ spr_register(env, SPR_VRSAVE, "VRSAVE",
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic,
0x00000000);
@@ -6990,38 +6990,38 @@ static void init_proc_POWER7 (CPUPPCState *env)
&spr_read_purr, SPR_NOACCESS,
&spr_read_purr, SPR_NOACCESS,
KVM_REG_PPC_SPURR, 0x00000000);
- spr_register(env, SPR_CFAR, "SPR_CFAR",
+ spr_register(env, SPR_CFAR, "CFAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_cfar, &spr_write_cfar,
0x00000000);
- spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
+ spr_register_kvm(env, SPR_DSCR, "DSCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_DSCR, 0x00000000);
- spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA",
+ spr_register_kvm(env, SPR_MMCRA, "MMCRA",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_MMCRA, 0x00000000);
- spr_register_kvm(env, SPR_PMC5, "SPR_PMC5",
+ spr_register_kvm(env, SPR_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_PMC5, 0x00000000);
- spr_register_kvm(env, SPR_PMC6, "SPR_PMC6",
+ spr_register_kvm(env, SPR_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_PMC6, 0x00000000);
#endif /* !CONFIG_USER_ONLY */
gen_spr_amr(env);
/* XXX : not implemented */
- spr_register(env, SPR_CTRL, "SPR_CTRLT",
+ spr_register(env, SPR_CTRL, "CTRLT",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, &spr_write_generic,
0x80800000);
- spr_register(env, SPR_UCTRL, "SPR_CTRLF",
+ spr_register(env, SPR_UCTRL, "CTRLF",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x80800000);
- spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
+ spr_register(env, SPR_VRSAVE, "VRSAVE",
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic,
0x00000000);
--
1.8.4.rc4
- [Qemu-ppc] [PATCH v2] target-ppc: improve "info registers" by printing SPRs,
Alexey Kardashevskiy <=
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2] target-ppc: improve "info registers" by printing SPRs, Stuart Brady, 2014/03/22
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2] target-ppc: improve "info registers" by printing SPRs, Alexey Kardashevskiy, 2014/03/24
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2] target-ppc: improve "info registers" by printing SPRs, Alexey Kardashevskiy, 2014/03/30
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2] target-ppc: improve "info registers" by printing SPRs, Andreas Färber, 2014/03/31
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2] target-ppc: improve "info registers" by printing SPRs, Alexey Kardashevskiy, 2014/03/31
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2] target-ppc: improve "info registers" by printing SPRs, Peter Maydell, 2014/03/31
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2] target-ppc: improve "info registers" by printing SPRs, Alexey Kardashevskiy, 2014/03/31
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2] target-ppc: improve "info registers" by printing SPRs, Alexander Graf, 2014/03/31
- Re: [Qemu-ppc] [Qemu-devel] [PATCH v2] target-ppc: improve "info registers" by printing SPRs, Stuart Brady, 2014/03/31