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[Qemu-ppc] [PATCH 8/8] ppc: Print HSRR0/HSRR1 in "info registers"
From: |
Cédric Le Goater |
Subject: |
[Qemu-ppc] [PATCH 8/8] ppc: Print HSRR0/HSRR1 in "info registers" |
Date: |
Mon, 27 Jun 2016 08:55:21 +0200 |
From: Benjamin Herrenschmidt <address@hidden>
They are generally useful when debugging HV mode stuff
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: fixed checkpatch.pl errors ]
Signed-off-by: Cédric Le Goater <address@hidden>
---
target-ppc/translate.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 2f1c59166eda..49fe76140708 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -11407,6 +11407,13 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf,
env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
+#if defined(TARGET_PPC64)
+ if (env->excp_model == POWERPC_EXCP_POWER7 ||
+ env->excp_model == POWERPC_EXCP_POWER8) {
+ cpu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
+ env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
+ }
+#endif
if (env->excp_model == POWERPC_EXCP_BOOKE) {
cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
" MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
--
2.1.4
- [Qemu-ppc] [PATCH 0/8] pnv: more fixes to the exception model, Cédric Le Goater, 2016/06/27
- [Qemu-ppc] [PATCH 1/8] ppc: Add a bunch of hypervisor SPRs to Book3s, Cédric Le Goater, 2016/06/27
- [Qemu-ppc] [PATCH 2/8] ppc: Update LPCR definitions, Cédric Le Goater, 2016/06/27
- [Qemu-ppc] [PATCH 3/8] ppc: Use a helper to filter writes to LPCR, Cédric Le Goater, 2016/06/27
- [Qemu-ppc] [PATCH 4/8] ppc: Fix conditions for delivering external interrupts to a guest, Cédric Le Goater, 2016/06/27
- [Qemu-ppc] [PATCH 5/8] ppc: Enforce setting MSR:EE, IR and DR when MSR:PR is set, Cédric Le Goater, 2016/06/27
- [Qemu-ppc] [PATCH 6/8] ppc: Initial HDEC support, Cédric Le Goater, 2016/06/27
- [Qemu-ppc] [PATCH 7/8] ppc: LPCR is a HV resource, Cédric Le Goater, 2016/06/27
- [Qemu-ppc] [PATCH 8/8] ppc: Print HSRR0/HSRR1 in "info registers",
Cédric Le Goater <=
- Re: [Qemu-ppc] [PATCH 0/8] pnv: more fixes to the exception model, David Gibson, 2016/06/28