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[Qemu-ppc] [RFC v2 08/13] target-ppc: add cnttzw[.] instruction
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-ppc] [RFC v2 08/13] target-ppc: add cnttzw[.] instruction |
Date: |
Sat, 23 Jul 2016 14:14:45 +0530 |
Add ISA3.0: Count trailing zeros word instruction.
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 5 +++++
target-ppc/translate.c | 11 +++++++++++
3 files changed, 17 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 8a3eb5d..3b3dc36 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -38,6 +38,7 @@ DEF_HELPER_4(divweu, tl, env, tl, tl, i32)
DEF_HELPER_4(divwe, tl, env, tl, tl, i32)
DEF_HELPER_FLAGS_1(cntlzw, TCG_CALL_NO_RWG_SE, tl, tl)
+DEF_HELPER_FLAGS_1(cnttzw, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 1d02e8a..ac47230 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -160,6 +160,11 @@ target_ulong helper_cntlzw(target_ulong t)
return clz32(t);
}
+target_ulong helper_cnttzw(target_ulong t)
+{
+ return ctz32(t);
+}
+
#if defined(TARGET_PPC64)
uint64_t helper_modsd(uint64_t rau, uint64_t rbu)
{
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 1fc1922..c28ddff 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1520,6 +1520,16 @@ static void gen_cntlzw(DisasContext *ctx)
if (unlikely(Rc(ctx->opcode) != 0))
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
+
+/* cnttzw */
+static void gen_cnttzw(DisasContext *ctx)
+{
+ gen_helper_cnttzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
+ }
+}
+
/* eqv & eqv. */
GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
/* extsb & extsb. */
@@ -9994,6 +10004,7 @@ GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000,
PPC_INTEGER),
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
+GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
--
2.7.4
- [Qemu-ppc] [RFC v2 04/13] target-ppc: add cmprb instruction, (continued)
[Qemu-ppc] [RFC v2 06/13] target-ppc: add modulo dword operations, Nikunj A Dadhania, 2016/07/23
[Qemu-ppc] [RFC v2 08/13] target-ppc: add cnttzw[.] instruction,
Nikunj A Dadhania <=
[Qemu-ppc] [RFC v2 09/13] target-ppc: add cmpeqb instruction, Nikunj A Dadhania, 2016/07/23
[Qemu-ppc] [RFC v2 10/13] target-ppc: add setb instruction, Nikunj A Dadhania, 2016/07/23
[Qemu-ppc] [RFC v2 07/13] target-ppc: add cnttzd[.] instruction, Nikunj A Dadhania, 2016/07/23
[Qemu-ppc] [RFC v2 11/13] target-ppc: add maddld instruction, Nikunj A Dadhania, 2016/07/23
[Qemu-ppc] [RFC v2 12/13] target-ppc: add maddhd and maddhdu instruction, Nikunj A Dadhania, 2016/07/23