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[Qemu-ppc] [PATCH 25/32] ppc: Handle unconditional (always/never) traps
From: |
Benjamin Herrenschmidt |
Subject: |
[Qemu-ppc] [PATCH 25/32] ppc: Handle unconditional (always/never) traps at translation time |
Date: |
Wed, 27 Jul 2016 08:21:19 +1000 |
We don't need to call a helper for trap always and trap never
which are used by Linux under some circumstances.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
---
target-ppc/translate.c | 48 ++++++++++++++++++++++++++++++++++++++++++------
1 file changed, 42 insertions(+), 6 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 9af3f5f..57a891b 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3360,10 +3360,29 @@ static void gen_sc(DisasContext *ctx)
/*** Trap ***/
+/* Check for unconditional traps (always or never) */
+static bool check_unconditional_trap(DisasContext *ctx)
+{
+ /* Trap never */
+ if (TO(ctx->opcode) == 0) {
+ return true;
+ }
+ /* Trap always */
+ if (TO(ctx->opcode) == 31) {
+ gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
+ }
+ return false;
+}
+
/* tw */
static void gen_tw(DisasContext *ctx)
{
- TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
+ TCGv_i32 t0;
+
+ if (check_unconditional_trap(ctx)) {
+ return;
+ }
+ t0 = tcg_const_i32(TO(ctx->opcode));
gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
t0);
tcg_temp_free_i32(t0);
@@ -3372,8 +3391,14 @@ static void gen_tw(DisasContext *ctx)
/* twi */
static void gen_twi(DisasContext *ctx)
{
- TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
- TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
+ TCGv t0;
+ TCGv_i32 t1;
+
+ if (check_unconditional_trap(ctx)) {
+ return;
+ }
+ t0 = tcg_const_tl(SIMM(ctx->opcode));
+ t1 = tcg_const_i32(TO(ctx->opcode));
gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
tcg_temp_free(t0);
tcg_temp_free_i32(t1);
@@ -3383,7 +3408,12 @@ static void gen_twi(DisasContext *ctx)
/* td */
static void gen_td(DisasContext *ctx)
{
- TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
+ TCGv_i32 t0;
+
+ if (check_unconditional_trap(ctx)) {
+ return;
+ }
+ t0 = tcg_const_i32(TO(ctx->opcode));
gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
t0);
tcg_temp_free_i32(t0);
@@ -3392,8 +3422,14 @@ static void gen_td(DisasContext *ctx)
/* tdi */
static void gen_tdi(DisasContext *ctx)
{
- TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
- TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
+ TCGv t0;
+ TCGv_i32 t1;
+
+ if (check_unconditional_trap(ctx)) {
+ return;
+ }
+ t0 = tcg_const_tl(SIMM(ctx->opcode));
+ t1 = tcg_const_i32(TO(ctx->opcode));
gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
tcg_temp_free(t0);
tcg_temp_free_i32(t1);
--
2.7.4
- [Qemu-ppc] [PATCH 22/32] ppc: Don't update NIP if not taking alignment exceptions, (continued)
- [Qemu-ppc] [PATCH 22/32] ppc: Don't update NIP if not taking alignment exceptions, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 26/32] ppc: Speed up dcbz, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 32/32] ppc: Speed up load/store multiple, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 14/32] ppc: Don't update NIP in lmw/stmw/icbi, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 23/32] ppc: Don't update NIP in dcbz and lscbx, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 17/32] ppc: Fix source NIP on SLB related interrupts, Benjamin Herrenschmidt, 2016/07/26
- [Qemu-ppc] [PATCH 25/32] ppc: Handle unconditional (always/never) traps at translation time,
Benjamin Herrenschmidt <=
- Re: [Qemu-ppc] [PATCH 01/32] ppc: Fix fault PC reporting for lve*/stve* VMX instructions, David Gibson, 2016/07/26