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Re: [Qemu-ppc] [RFC PATCH 13/17] target/ppc/POWER9: Add cpu_has_work fun
From: |
David Gibson |
Subject: |
Re: [Qemu-ppc] [RFC PATCH 13/17] target/ppc/POWER9: Add cpu_has_work function for POWER9 |
Date: |
Wed, 1 Feb 2017 15:34:41 +1100 |
User-agent: |
Mutt/1.7.1 (2016-10-04) |
On Fri, Jan 13, 2017 at 05:28:19PM +1100, Suraj Jitindar Singh wrote:
> The cpu has work function is used to mask interrupts used to determine
> if there is work for the cpu based on the LPCR. Add a function to do this
> for POWER9 and add it to the POWER9 cpu definition. This is similar to that
> for POWER8 except using the LPCR bits as defined for POWER9.
>
> Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
> ---
> target/ppc/translate_init.c | 45
> +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index 87297a7..9db004d 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -8797,10 +8797,54 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass
> *pcc, uint32_t pvr)
> return false;
> }
>
> +static bool cpu_has_work_POWER9(CPUState *cs)
> +{
> + PowerPCCPU *cpu = POWERPC_CPU(cs);
> + CPUPPCState *env = &cpu->env;
> +
> + if (cs->halted) {
> + if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
> + return false;
> + }
> + /* External Exception */
> + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
> + (env->spr[SPR_LPCR] & LPCR_EEE)) {
> + return true;
> + }
> + /* Decrementer Exception */
> + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
> + (env->spr[SPR_LPCR] & LPCR_DEE)) {
> + return true;
> + }
> + /* Machine Check or Hypervisor Maintenance Exception */
> + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
> + 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
> + return true;
> + }
> + /* Privileged Doorbell Exception */
> + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
> + (env->spr[SPR_LPCR] & LPCR_PDEE)) {
> + return true;
> + }
> + /* Hypervisor Doorbell Exception */
> + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
> + (env->spr[SPR_LPCR] & LPCR_HDEE)) {
> + return true;
> + }
> + if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
> + return true;
> + }
> + return false;
> + } else {
> + return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
> + }
> +}
> +
> POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> + CPUClass *cc = CPU_CLASS(oc);
>
> dc->fw_name = "PowerPC,POWER9";
> dc->desc = "POWER9";
> @@ -8811,6 +8855,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
> PCR_COMPAT_2_05;
> pcc->init_proc = init_proc_POWER9;
> pcc->check_pow = check_pow_nocheck;
> + cc->has_work = cpu_has_work_POWER9;
> pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
> PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
> PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [Qemu-ppc] [RFC PATCH 07/17] target/ppc/POWER9: Add partition table pointer to sPAPRMachineState, (continued)
- [Qemu-ppc] [RFC PATCH 09/17] target/ppc/POWER9: Remove SDR1 register, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 10/17] target/ppc/POWER9: Add POWER9 mmu fault handler, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 12/17] target/ppc/POWER9: Add POWER9 pa-features definition, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 11/17] target/ppc/POWER9: Update to new pte format for POWER9 accesses, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 13/17] target/ppc/POWER9: Add cpu_has_work function for POWER9, Suraj Jitindar Singh, 2017/01/13
- Re: [Qemu-ppc] [RFC PATCH 13/17] target/ppc/POWER9: Add cpu_has_work function for POWER9,
David Gibson <=
- [Qemu-ppc] [RFC PATCH 14/17] target/ppc/debug: Print LPCR register value if register exists, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 15/17] tcg/POWER9: NOOP the cp_abort instruction, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 16/17] target/ppc/mmu_hash64: Fix printing unsigned as signed int, Suraj Jitindar Singh, 2017/01/13
- [Qemu-ppc] [RFC PATCH 17/17] target/ppc/mmu_hash64: Fix incorrect shift value in amr calculation, Suraj Jitindar Singh, 2017/01/13
- Re: [Qemu-ppc] [Qemu-devel] [RFC PATCH 00/17] target/ppc: Implement POWER9 pseries tcg legacy kernel support, no-reply, 2017/01/13
- Re: [Qemu-ppc] [RFC PATCH 00/17] target/ppc: Implement POWER9 pseries tcg legacy kernel support, David Gibson, 2017/01/31