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Re: [Qemu-ppc] [RFC PATCH v2 11/21] ppc/xive: push the EQ data in OS eve
From: |
Benjamin Herrenschmidt |
Subject: |
Re: [Qemu-ppc] [RFC PATCH v2 11/21] ppc/xive: push the EQ data in OS event queue |
Date: |
Thu, 28 Sep 2017 10:12:39 +0200 |
On Wed, 2017-09-20 at 16:34 +1000, David Gibson wrote:
> > >> + if (GETFIELD(EQ_W6_FORMAT_BIT, eq->w6) == 0) {
> > >> + priority = GETFIELD(EQ_W7_F0_PRIORITY, eq->w7);
> > >>
> > >> + /* The EQ is masked. Can this happen ? */
> > >> + if (priority == 0xff) {
> > >> + return;
> > >
> > > How does the 8-bit priority field here interact with the 3-bit
> > > priority which selects which EQ to use?
> >
> > priority OxFF is a special case kept for masking, see the hcall
> > h_int_set_source_config. It should never reach the EQ lookup
> > routines. So may be an assert would be better here.
>
> Ok, if this situation can't be guest triggered, only by a bug in the
> rest of the XIVE code, then an assert() is better.
Note: this doesn't match HW. However there's a mask bit in the EAS.
The problem when masking that way of course is that you lose triggers,
ie P gets set, the interrupt lost, and nobody will clear P.
Cheers,
Ben.
- [Qemu-ppc] [RFC PATCH v2 09/21] ppc/xive: extend the interrupt presenter model for XIVE, (continued)
[Qemu-ppc] [RFC PATCH v2 10/21] ppc/xive: add MMIO handlers for the XIVE TIMA, Cédric Le Goater, 2017/09/11
[Qemu-ppc] [RFC PATCH v2 11/21] ppc/xive: push the EQ data in OS event queue, Cédric Le Goater, 2017/09/11
[Qemu-ppc] [RFC PATCH v2 12/21] ppc/xive: notify the CPU when interrupt priority is more privileged, Cédric Le Goater, 2017/09/11
[Qemu-ppc] [RFC PATCH v2 13/21] ppc/xive: handle interrupt acknowledgment by the O/S, Cédric Le Goater, 2017/09/11
[Qemu-ppc] [RFC PATCH v2 14/21] ppc/xive: add support for the SET_OS_PENDING command, Cédric Le Goater, 2017/09/11