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[PULL 10/19] ppc/pnv: Remove default disablement of the PNOR contents
From: |
David Gibson |
Subject: |
[PULL 10/19] ppc/pnv: Remove default disablement of the PNOR contents |
Date: |
Wed, 10 Feb 2021 17:17:26 +1100 |
From: Cédric Le Goater <clg@kaod.org>
On PowerNV systems, the BMC is in charge of mapping the PNOR contents
on the LPC FW address space using the HIOMAP protocol. Under QEMU, we
emulate this behavior and we also add an extra control on the flash
accesses by letting the HIOMAP command handler decide whether the
memory region is accessible or not depending on the firmware requests.
However, this behavior is not compatible with hostboot like firmwares
which need this mapping to be always available. For this reason, the
PNOR memory region is initially disabled for skiboot mode only.
This is badly placed under the LPC model and requires the use of the
machine. Since it doesn't add much, simply remove the initial setting.
The extra control in the HIOMAP command handler will still be performed.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20210126171059.307867-7-clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/pnv_lpc.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index 5903590220..11739e397b 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -825,7 +825,6 @@ ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool
use_cpld, Error **errp)
qemu_irq *irqs;
qemu_irq_handler handler;
PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
- bool hostboot_mode = !!pnv->fw_load_addr;
/* let isa_bus_new() create its own bridge on SysBus otherwise
* devices specified on the command line won't find the bus and
@@ -856,13 +855,6 @@ ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool
use_cpld, Error **errp)
*/
memory_region_add_subregion(&lpc->isa_fw, PNOR_SPI_OFFSET,
&pnv->pnor->mmio);
- /*
- * Start disabled. The HIOMAP protocol will activate the mapping
- * with HIOMAP_C_CREATE_WRITE_WINDOW
- */
- if (!hostboot_mode) {
- memory_region_set_enabled(&pnv->pnor->mmio, false);
- }
return isa_bus;
}
--
2.29.2
- [PULL 01/19] spapr.c: use g_auto* with 'nodename' in CPU DT functions, (continued)
- [PULL 01/19] spapr.c: use g_auto* with 'nodename' in CPU DT functions, David Gibson, 2021/02/10
- [PULL 02/19] spapr.c: add 'name' property for hotplugged CPUs nodes, David Gibson, 2021/02/10
- [PULL 03/19] spapr: Adjust firmware path of PCI devices, David Gibson, 2021/02/10
- [PULL 04/19] target/ppc: Remove unused MMU definitions, David Gibson, 2021/02/10
- [PULL 08/19] ppc/pnv: Simplify pnv_bmc_create(), David Gibson, 2021/02/10
- [PULL 09/19] ppc/pnv: Discard internal BMC initialization when BMC is external, David Gibson, 2021/02/10
- [PULL 14/19] spapr_numa.c: fix ibm, max-associativity-domains calculation, David Gibson, 2021/02/10
- [PULL 06/19] ppc/xive: Add firmware bit when dumping the ENDs, David Gibson, 2021/02/10
- [PULL 05/19] ppc/pnv: Add trace events for PCI event notification, David Gibson, 2021/02/10
- [PULL 07/19] ppc/pnv: Use skiboot addresses to load kernel and ramfs, David Gibson, 2021/02/10
- [PULL 10/19] ppc/pnv: Remove default disablement of the PNOR contents,
David Gibson <=
- [PULL 12/19] spapr: move spapr_machine_using_legacy_numa() to spapr_numa.c, David Gibson, 2021/02/10
- [PULL 11/19] ppc/pnv: Introduce a LPC FW memory region attribute to map the PNOR, David Gibson, 2021/02/10
- [PULL 16/19] hw/ppc: e500: Use a macro for the platform clock frequency, David Gibson, 2021/02/10
- [PULL 18/19] hw/net: fsl_etsec: Reverse the RCTRL.RSF logic, David Gibson, 2021/02/10
- [PULL 19/19] target/ppc: Add E500 L2CSR0 write helper, David Gibson, 2021/02/10
- [PULL 13/19] spapr_numa.c: create spapr_numa_initial_nvgpu_numa_id() helper, David Gibson, 2021/02/10
- [PULL 15/19] ppc/pnv: Set default RAM size to 1 GB, David Gibson, 2021/02/10
- [PULL 17/19] hw/ppc: e500: Fill in correct <clock-frequency> for the serial nodes, David Gibson, 2021/02/10
- Re: [PULL 00/19] ppc-for-6.0 queue 20210210, Peter Maydell, 2021/02/10