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[PATCH v2 07/34] target/ppc: Implement cntlzdm
From: |
matheus . ferst |
Subject: |
[PATCH v2 07/34] target/ppc: Implement cntlzdm |
Date: |
Fri, 29 Oct 2021 17:23:57 -0300 |
From: Luis Pires <luis.pires@eldorado.org.br>
Implement the following PowerISA v3.1 instruction:
cntlzdm: Count Leading Zeros Doubleword Under Bit Mask
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v2:
- Inline implementation of cntlzdm
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/fixedpoint-impl.c.inc | 36 ++++++++++++++++++++++
2 files changed, 37 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 9cb9fc00b8..221cb00dd6 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -203,6 +203,7 @@ ADDPCIS 010011 ..... ..... .......... 00010 . @DX
## Fixed-Point Logical Instructions
CFUGED 011111 ..... ..... ..... 0011011100 - @X
+CNTLZDM 011111 ..... ..... ..... 0000111011 - @X
### Float-Point Load Instructions
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index 0d9c6e0996..c9e9ae35df 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -413,3 +413,39 @@ static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
#endif
return true;
}
+
+#if defined(TARGET_PPC64)
+static void do_cntlzdm(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 mask)
+{
+ TCGv_i64 tmp;
+ TCGLabel *l1;
+
+ tmp = tcg_temp_local_new_i64();
+ l1 = gen_new_label();
+
+ tcg_gen_and_i64(tmp, src, mask);
+ tcg_gen_clzi_i64(tmp, tmp, 64);
+
+ tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1);
+
+ tcg_gen_subfi_i64(tmp, 64, tmp);
+ tcg_gen_shr_i64(tmp, mask, tmp);
+ tcg_gen_ctpop_i64(tmp, tmp);
+
+ gen_set_label(l1);
+
+ tcg_gen_mov_i64(dst, tmp);
+}
+#endif
+
+static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+#if defined(TARGET_PPC64)
+ do_cntlzdm(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
--
2.25.1
- [PATCH v2 00/34] PowerISA v3.1 instruction batch, matheus . ferst, 2021/10/29
- [PATCH v2 03/34] target/ppc: Move load and store floating point instructions to decodetree, matheus . ferst, 2021/10/29
- [PATCH v2 01/34] target/ppc: introduce do_ea_calc, matheus . ferst, 2021/10/29
- [PATCH v2 06/34] target/ppc: Implement PLQ and PSTQ, matheus . ferst, 2021/10/29
- [PATCH v2 02/34] target/ppc: move resolve_PLS_D to translate.c, matheus . ferst, 2021/10/29
- [PATCH v2 04/34] target/ppc: Implement PLFS, PLFD, PSTFS and PSTFD instructions, matheus . ferst, 2021/10/29
- [PATCH v2 07/34] target/ppc: Implement cntlzdm,
matheus . ferst <=
- [PATCH v2 05/34] target/ppc: Move LQ and STQ to decodetree, matheus . ferst, 2021/10/29
- [PATCH v2 08/34] target/ppc: Implement cnttzdm, matheus . ferst, 2021/10/29
- [PATCH v2 09/34] target/ppc: Implement pdepd instruction, matheus . ferst, 2021/10/29
- [PATCH v2 10/34] target/ppc: Implement pextd instruction, matheus . ferst, 2021/10/29
- [PATCH v2 11/34] target/ppc: Move vcfuged to vmx-impl.c.inc, matheus . ferst, 2021/10/29
- [PATCH v2 12/34] target/ppc: Implement vclzdm/vctzdm instructions, matheus . ferst, 2021/10/29