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[PULL 28/34] target/ppc: Add flag for ISA v2.06 BCDA instructions
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 28/34] target/ppc: Add flag for ISA v2.06 BCDA instructions |
Date: |
Wed, 6 Jul 2022 17:09:40 -0300 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Adds an insns_flags2 for the BCD assist instructions introduced in
Power ISA 2.06. These instructions are not listed in the manuals for
e5500[1] and e6500[2], so the flag is only added for POWER7/8/9/10
models.
[1] https://www.nxp.com/files-static/32bit/doc/ref_manual/EREF_RM.pdf
[2] https://www.nxp.com/docs/en/reference-manual/E6500RM.pdf
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: VĂctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220629162904.105060-9-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/cpu.h | 5 ++++-
target/ppc/cpu_init.c | 10 ++++++----
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index b38c651af4..7aaff9dcc5 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2289,6 +2289,8 @@ enum {
PPC2_ISA310 = 0x0000000000100000ULL,
/* lwsync instruction */
PPC2_MEM_LWSYNC = 0x0000000000200000ULL,
+ /* ISA 2.06 BCD assist instructions */
+ PPC2_BCDA_ISA206 = 0x0000000000400000ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
@@ -2297,7 +2299,8 @@ enum {
PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
- PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC)
+ PPC2_ISA300 | PPC2_ISA310 | PPC2_MEM_LWSYNC | \
+ PPC2_BCDA_ISA206)
};
/*****************************************************************************/
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index c16cb8dbe7..bdfb1a5c6f 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5985,7 +5985,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 |
- PPC2_PM_ISA206 | PPC2_MEM_LWSYNC;
+ PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_VR) |
(1ull << MSR_VSX) |
@@ -6159,7 +6159,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
- PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC;
+ PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC |
+ PPC2_BCDA_ISA206;
pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_HV) |
(1ull << MSR_TM) |
@@ -6379,7 +6380,8 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
- PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_MEM_LWSYNC;
+ PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_MEM_LWSYNC |
+ PPC2_BCDA_ISA206;
pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_HV) |
(1ull << MSR_TM) |
@@ -6597,7 +6599,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 |
- PPC2_MEM_LWSYNC;
+ PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206;
pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_HV) |
(1ull << MSR_TM) |
--
2.36.1
- [PULL 12/34] target/ppc: use int128.h methods in vpmsumd, (continued)
- [PULL 12/34] target/ppc: use int128.h methods in vpmsumd, Daniel Henrique Barboza, 2022/07/06
- [PULL 13/34] target/ppc: use int128.h methods in vadduqm, Daniel Henrique Barboza, 2022/07/06
- [PULL 21/34] target/ppc: Fix insn32.decode style issues, Daniel Henrique Barboza, 2022/07/06
- [PULL 18/34] target/ppc: use int128.h methods in vsubcuq, Daniel Henrique Barboza, 2022/07/06
- [PULL 17/34] target/ppc: use int128.h methods in vsubecuq and vsubeuqm, Daniel Henrique Barboza, 2022/07/06
- [PULL 15/34] target/ppc: use int128.h methods in vaddcuq, Daniel Henrique Barboza, 2022/07/06
- [PULL 24/34] target/ppc: Move mffsl to decodetree, Daniel Henrique Barboza, 2022/07/06
- [PULL 29/34] target/ppc: implement addg6s, Daniel Henrique Barboza, 2022/07/06
- [PULL 25/34] target/ppc: Move mffs[.] to decodetree, Daniel Henrique Barboza, 2022/07/06
- [PULL 22/34] target/ppc: Move mffscrn[i] to decodetree, Daniel Henrique Barboza, 2022/07/06
- [PULL 28/34] target/ppc: Add flag for ISA v2.06 BCDA instructions,
Daniel Henrique Barboza <=
- [PULL 27/34] tests/tcg/ppc64: Add mffsce test, Daniel Henrique Barboza, 2022/07/06
- [PULL 23/34] target/ppc: Move mffsce to decodetree, Daniel Henrique Barboza, 2022/07/06
- [PULL 26/34] target/ppc: Implement mffscdrn[i] instructions, Daniel Henrique Barboza, 2022/07/06
- [PULL 30/34] target/ppc: implement cbcdtd, Daniel Henrique Barboza, 2022/07/06
- [PULL 31/34] target/ppc: implement cdtbcd, Daniel Henrique Barboza, 2022/07/06
- [PULL 33/34] target/ppc/cpu-models: Remove the "default" CPU alias, Daniel Henrique Barboza, 2022/07/06
- [PULL 32/34] target/ppc: Return default CPU for max CPU, Daniel Henrique Barboza, 2022/07/06
- [PULL 34/34] target/ppc: Fix MPC8555 and MPC8560 core type to e500v1, Daniel Henrique Barboza, 2022/07/06
- Re: [PULL 00/34] ppc queue, Richard Henderson, 2022/07/06