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[PULL 21/30] target/ppc: Add initial flags and helpers for SMT support
From: |
Cédric Le Goater |
Subject: |
[PULL 21/30] target/ppc: Add initial flags and helpers for SMT support |
Date: |
Mon, 26 Jun 2023 07:56:38 +0200 |
From: Nicholas Piggin <npiggin@gmail.com>
TGC SMT emulation needs to know whether it is running with SMT siblings,
to be able to iterate over siblings in a core, and to serialise
threads to access per-core shared SPRs. Add infrastructure to do these
things.
For now the sibling iteration and serialisation are implemented in a
simple but inefficient way. SMT shared state and sibling access is not
too common, and SMT configurations are mainly useful to test system
code, so performance is not to critical.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: fix build breakage with clang ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 9 +++++++++
target/ppc/cpu_init.c | 5 +++++
target/ppc/translate.c | 22 ++++++++++++++++++++++
3 files changed, 36 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 054edf3c8014..4138a2580109 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -672,6 +672,8 @@ enum {
POWERPC_FLAG_TM = 0x00100000,
/* Has SCV (ISA 3.00) */
POWERPC_FLAG_SCV = 0x00200000,
+ /* Has >1 thread per core */
+ POWERPC_FLAG_SMT = 0x00400000,
};
/*
@@ -1268,6 +1270,13 @@ struct CPUArchState {
uint64_t pmu_base_time;
};
+#define _CORE_ID(cs) \
+ (POWERPC_CPU(cs)->env.spr_cb[SPR_PIR].default_value & ~(cs->nr_threads -
1))
+
+#define THREAD_SIBLING_FOREACH(cs, cs_sibling) \
+ CPU_FOREACH(cs_sibling) \
+ if (_CORE_ID(cs) == _CORE_ID(cs_sibling))
+
#define SET_FIT_PERIOD(a_, b_, c_, d_) \
do { \
env->fit_period[0] = (a_); \
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index dccc06405381..aeff71d063d2 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6755,6 +6755,7 @@ static void ppc_cpu_realize(DeviceState *dev, Error
**errp)
{
CPUState *cs = CPU(dev);
PowerPCCPU *cpu = POWERPC_CPU(dev);
+ CPUPPCState *env = &cpu->env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
Error *local_err = NULL;
@@ -6786,6 +6787,10 @@ static void ppc_cpu_realize(DeviceState *dev, Error
**errp)
pcc->parent_realize(dev, errp);
+ if (env_cpu(env)->nr_threads > 1) {
+ env->flags |= POWERPC_FLAG_SMT;
+ }
+
return;
unrealize:
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 8f74a864e48e..7d8877b3dcfd 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -234,6 +234,28 @@ struct opc_handler_t {
void (*handler)(DisasContext *ctx);
};
+static inline bool gen_serialize(DisasContext *ctx)
+{
+ if (tb_cflags(ctx->base.tb) & CF_PARALLEL) {
+ /* Restart with exclusive lock. */
+ gen_helper_exit_atomic(cpu_env);
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return false;
+ }
+ return true;
+}
+
+#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+static inline bool gen_serialize_core(DisasContext *ctx)
+{
+ if (ctx->flags & POWERPC_FLAG_SMT) {
+ return gen_serialize(ctx);
+ }
+
+ return true;
+}
+#endif
+
/* SPR load/store helpers */
static inline void gen_load_spr(TCGv t, int reg)
{
--
2.41.0
- [PULL 11/30] ppc/spapr: Add a nested state struct, (continued)
- [PULL 11/30] ppc/spapr: Add a nested state struct, Cédric Le Goater, 2023/06/26
- [PULL 09/30] target/ppc: Fix timer register accessors when !KVM, Cédric Le Goater, 2023/06/26
- [PULL 10/30] ppc/spapr: H_ENTER_NESTED should restore host XER ca field, Cédric Le Goater, 2023/06/26
- [PULL 13/30] ppc/spapr: Move spapr nested HV to a new file, Cédric Le Goater, 2023/06/26
- [PULL 17/30] target/ppc: Implement HEIR SPR, Cédric Le Goater, 2023/06/26
- [PULL 14/30] target/ppc: Fix instruction loading endianness in alignment interrupt, Cédric Le Goater, 2023/06/26
- [PULL 12/30] ppc/spapr: load and store l2 state with helper functions, Cédric Le Goater, 2023/06/26
- [PULL 15/30] target/ppc: Change partition-scope translate interface, Cédric Le Goater, 2023/06/26
- [PULL 16/30] target/ppc: Add SRR1 prefix indication to interrupt handlers, Cédric Le Goater, 2023/06/26
- [PULL 23/30] target/ppc: Add msgsnd/p and DPDES SMT support, Cédric Le Goater, 2023/06/26
- [PULL 21/30] target/ppc: Add initial flags and helpers for SMT support,
Cédric Le Goater <=
- [PULL 24/30] hw/ppc/spapr: Test whether TCG is enabled with tcg_enabled(), Cédric Le Goater, 2023/06/26
- [PULL 26/30] tests/avocado: boot ppc64 pseries to Linux VFS mount, Cédric Le Goater, 2023/06/26
- [PULL 19/30] target/ppc: Better CTRL SPR implementation, Cédric Le Goater, 2023/06/26
- [PULL 29/30] pnv/xive2: Check TIMA special ops against a dedicated array for P10, Cédric Le Goater, 2023/06/26
- [PULL 22/30] target/ppc: Add support for SMT CTRL register, Cédric Le Goater, 2023/06/26
- [PULL 18/30] target/ppc: Add ISA v3.1 LEV indication in SRR1 for system call interrupts, Cédric Le Goater, 2023/06/26
- [PULL 20/30] target/ppc: Fix sc instruction handling of LEV field, Cédric Le Goater, 2023/06/26
- [PULL 25/30] spapr: TCG allow up to 8-thread SMT on POWER8 and newer CPUs, Cédric Le Goater, 2023/06/26
- [PULL 28/30] pnv/xive2: Add a get_config() method on the presenter class, Cédric Le Goater, 2023/06/26
- [PULL 27/30] tests/avocado: Add ppc64 pseries multiprocessor boot tests, Cédric Le Goater, 2023/06/26