The following changes since commit 97c81ef4b8e203d9620fd46e7eb77004563e3675:
Merge tag 'pull-9p-20230706' of https://github.com/cschoenebeck/qemu into
staging (2023-07-06 18:19:42 +0100)
are available in the Git repository at:
https://gitlab.com/danielhb/qemu.git tags/pull-ppc-20230707
for you to fetch changes up to 2f8ebb98ef8c7e85b23678812d8a7a95c9479673:
ppc: Enable 2nd DAWR support on p10 (2023-07-07 06:33:04 -0300)
----------------------------------------------------------------
ppc patch queue for 2023-07-07:
In this last queue for 8.1 we have a lot of fixes and improvements all
around: SMT support for powerNV, XIVE fixes, PPC440 cleanups, exception
handling cleanups and kvm_pph.h cleanups just to name a few.
Thanks everyone in the qemu-ppc community for all the contributions for
the next QEMU release.
----------------------------------------------------------------
BALATON Zoltan (22):
mv64361: Add dummy gigabit ethernet PHY access registers
target/ppc: Remove some superfluous parentheses
target/ppc: Remove unneeded parameter from powerpc_reset_wakeup()
target/ppc: Move common check in exception handlers to a function
target/ppc: Remove some more local CPUState variables only used once
target/ppd: Remove unused define
target/ppc: Get CPUState in one step
ppc/pegasos2: Add support for -initrd command line option
ppc440: Change ppc460ex_pcie_init() parameter type
ppc440: Add cpu link property to PCIe controller model
ppc440: Add a macro to shorten PCIe controller DCR registration
ppc440: Rename parent field of PPC460EXPCIEState to match code style
ppc440: Rename local variable in dcr_read_pcie()
ppc440: Stop using system io region for PCIe buses
ppc440: Add busnum property to PCIe controller model
ppc440: Remove ppc460ex_pcie_init legacy init function
ppc/sam460ex: Remove address_space_mem local variable
ppc440_pcix: Don't use iomem for regs
ppc440_pcix: Stop using system io region for PCI bus
ppc4xx_pci: Rename QOM type name define
ppc4xx_pci: Add define for ppc4xx-host-bridge type name
ppc440_pcix: Rename QOM type define abd move it to common header
Frederic Barrat (8):
pnv/psi: Allow access to PSI registers through xscom
pnv/xive2: Allow indirect TIMA accesses of all sizes
pnv/xive2: Fix TIMA offset for indirect access
pnv/xive: Add property on xive sources to define PQ state on reset
pnv/psi: Initialize the PSIHB interrupts to match hardware
pnv/xive: Allow mmio operations of any size on the ESB CI pages
pnv/xive: Print CPU target in all TIMA traces
pnv/xive2: Always pass a presenter object when accessing the TIMA
Joel Stanley (7):
ppc/pnv: quad xscom callbacks are P9 specific
ppc/pnv: Subclass quad xscom callbacks
ppc/pnv: Add P10 quad xscom model
ppc/pnv: Add P10 core xscom model
ppc/pnv: Return zero for core thread state xscom
ppc/pnv: Log all unimp warnings with similar message
ppc/pnv: Add QME region for P10
Narayana Murty N (1):
target: ppc: Use MSR_HVB bit to get the target endianness for memory dump
Nicholas Piggin (14):
target/ppc: Make HDECR underflow edge triggered
hw/ppc: Fix clock update drift
target/ppc: Tidy POWER book4 SPR registration
target/ppc: Add TFMR SPR implementation with read and write helpers
sungem: Add WOL MMIO
target/ppc: Fix icount access for some hypervisor instructions
tests/avocado: record_replay test for ppc powernv machine
target/ppc: Add LPAR-per-core vs per-thread mode flag
target/ppc: SMT support for the HID SPR
ppc/pnv: SMT support for powernv
tests/avocado: Add powernv machine test script
ppc/pnv: Set P10 core xscom region size to match hardware
tests/qtest: Add xscom tests for powernv10 machine
target/ppc: Machine check on invalid real address access on POWER9/10
Philippe Mathieu-Daudé (7):
target/ppc: Only generate decodetree files when TCG is enabled
target/ppc: Have 'kvm_ppc.h' include 'sysemu/kvm.h'
target/ppc: Reorder #ifdef'ry in kvm_ppc.h
target/ppc: Move CPU QOM definitions to cpu-qom.h
target/ppc: Define TYPE_HOST_POWERPC_CPU in cpu-qom.h
target/ppc: Restrict 'kvm_ppc.h' to sysemu in cpu_init.c
target/ppc: Remove pointless checks of CONFIG_USER_ONLY in 'kvm_ppc.h'
Ravi Bangoria (1):
ppc: Enable 2nd DAWR support on p10
docs/system/ppc/powernv.rst | 5 -
hw/intc/pnv_xive2.c | 26 +++-
hw/intc/trace-events | 4 +-
hw/intc/xive.c | 20 +--
hw/intc/xive2.c | 4 +-
hw/net/sungem.c | 52 ++++++++
hw/net/trace-events | 2 +
hw/pci-host/mv64361.c | 6 +
hw/pci-host/mv643xx.h | 3 +
hw/ppc/pegasos2.c | 32 ++++-
hw/ppc/pnv.c | 26 +++-
hw/ppc/pnv_core.c | 282 ++++++++++++++++++++++++++++++++++-------
hw/ppc/pnv_psi.c | 33 +++--
hw/ppc/ppc.c | 49 +++----
hw/ppc/ppc440.h | 1 -
hw/ppc/ppc440_bamboo.c | 3 +-
hw/ppc/ppc440_pcix.c | 28 ++--
hw/ppc/ppc440_uc.c | 192 ++++++++++++----------------
hw/ppc/ppc4xx_pci.c | 10 +-
hw/ppc/sam460ex.c | 33 +++--
hw/ppc/spapr.c | 7 +-
hw/ppc/spapr_caps.c | 32 +++++
hw/ppc/spapr_cpu_core.c | 2 +
include/hw/ppc/pnv_core.h | 18 ++-
include/hw/ppc/pnv_xscom.h | 15 ++-
include/hw/ppc/ppc4xx.h | 5 +-
include/hw/ppc/spapr.h | 6 +-
include/hw/ppc/xive.h | 1 +
target/ppc/arch_dump.c | 2 +-
target/ppc/cpu-qom.h | 6 +
target/ppc/cpu.h | 9 +-
target/ppc/cpu_init.c | 112 ++++++++++++----
target/ppc/excp_helper.c | 206 ++++++++++++++----------------
target/ppc/helper.h | 3 +
target/ppc/internal.h | 5 +
target/ppc/kvm.c | 12 ++
target/ppc/kvm_ppc.h | 82 ++++++------
target/ppc/meson.build | 2 +-
target/ppc/misc_helper.c | 29 +++++
target/ppc/spr_common.h | 3 +
target/ppc/timebase_helper.c | 13 ++
target/ppc/translate.c | 45 ++++++-
tests/avocado/ppc_powernv.py | 87 +++++++++++++
tests/avocado/replay_kernel.py | 17 +++
tests/qtest/pnv-xscom-test.c | 45 +++++--
45 files changed, 1123 insertions(+), 452 deletions(-)
create mode 100644 tests/avocado/ppc_powernv.py