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[PATCH 08/26] target/ppc: Fix move-to timebase SPR access permissions
From: |
Nicholas Piggin |
Subject: |
[PATCH 08/26] target/ppc: Fix move-to timebase SPR access permissions |
Date: |
Fri, 19 Jan 2024 01:06:26 +1000 |
The move-to timebase registers TBU and TBL can not be read, and they
can not be written in supervisor mode on hypervisor-capable CPUs.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/helper_regs.c | 31 +++++++++++++++++++++++--------
1 file changed, 23 insertions(+), 8 deletions(-)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index ead4acede4..25258986e3 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -473,18 +473,33 @@ void register_generic_sprs(PowerPCCPU *cpu)
&spr_read_tbl, SPR_NOACCESS,
&spr_read_tbl, SPR_NOACCESS,
0x00000000);
- spr_register(env, SPR_WR_TBL, "TBL",
- &spr_read_tbl, SPR_NOACCESS,
- &spr_read_tbl, &spr_write_tbl,
- 0x00000000);
spr_register(env, SPR_TBU, "TBU",
&spr_read_tbu, SPR_NOACCESS,
&spr_read_tbu, SPR_NOACCESS,
0x00000000);
- spr_register(env, SPR_WR_TBU, "TBU",
- &spr_read_tbu, SPR_NOACCESS,
- &spr_read_tbu, &spr_write_tbu,
- 0x00000000);
+#ifndef CONFIG_USER_ONLY
+ if (env->has_hv_mode) {
+ spr_register_hv(env, SPR_WR_TBL, "TBL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_tbl,
+ 0x00000000);
+ spr_register_hv(env, SPR_WR_TBU, "TBU",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_tbu,
+ 0x00000000);
+ } else {
+ spr_register(env, SPR_WR_TBL, "TBL",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_tbl,
+ 0x00000000);
+ spr_register(env, SPR_WR_TBU, "TBU",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, &spr_write_tbu,
+ 0x00000000);
+ }
+#endif
}
void register_non_embedded_sprs(CPUPPCState *env)
--
2.42.0
- [PATCH 00/26] target/ppc: TCG improvements and fixes, Nicholas Piggin, 2024/01/18
- [PATCH 01/26] target/ppc: Fix crash on machine check caused by ifetch, Nicholas Piggin, 2024/01/18
- [PATCH 02/26] target/ppc: Prevent supervisor from modifying MSR[ME], Nicholas Piggin, 2024/01/18
- [PATCH 03/26] spapr: set MSR[ME] and MSR[FP] on client entry, Nicholas Piggin, 2024/01/18
- [PATCH 04/26] target/ppc: Rename registers to match ISA, Nicholas Piggin, 2024/01/18
- [PATCH 05/26] target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U, Nicholas Piggin, 2024/01/18
- [PATCH 06/26] target/ppc: Rename TBL to TB on 64-bit, Nicholas Piggin, 2024/01/18
- [PATCH 07/26] target/ppc: Improve timebase register defines naming, Nicholas Piggin, 2024/01/18
- [PATCH 08/26] target/ppc: Fix move-to timebase SPR access permissions,
Nicholas Piggin <=
- [PATCH 09/26] pnv/chiptod: Add POWER9/10 chiptod model, Nicholas Piggin, 2024/01/18
- [PATCH 10/26] ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines, Nicholas Piggin, 2024/01/18
- [PATCH 11/26] pnv/chiptod: Implement the ChipTOD to Core transfer, Nicholas Piggin, 2024/01/18
- [PATCH 12/26] target/ppc: Implement core timebase state machine and TFMR, Nicholas Piggin, 2024/01/18
- [PATCH 13/26] target/ppc: Add SMT support to time facilities, Nicholas Piggin, 2024/01/18
- [PATCH 14/26] target/ppc: Add new hflags to support BHRB, Nicholas Piggin, 2024/01/18
- [PATCH 15/26] target/ppc: Add recording of taken branches to BHRB, Nicholas Piggin, 2024/01/18
- [PATCH 17/26] target/ppc: Add migration support for BHRB, Nicholas Piggin, 2024/01/18
- [PATCH 18/26] target/ppc: BookE DECAR SPR is 32-bit, Nicholas Piggin, 2024/01/18
- [PATCH 16/26] target/ppc: Add clrbhrb and mfbhrbe instructions, Nicholas Piggin, 2024/01/18