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[PATCH v4 0/5] hw/ppc: SPI model
From: |
Chalapathi V |
Subject: |
[PATCH v4 0/5] hw/ppc: SPI model |
Date: |
Mon, 17 Jun 2024 11:54:14 -0500 |
Hello,
Thank You so much for reviewing patch v3.
In patch v4,
- Renamed hw/ppc/pnv_spi_controller.c to /hw/ssi/pnv_spi.c
- To improve the readability register/field names is shortened.
- SPI registers are put in array to simplify read/write method.
- In seeprom qtest generated the tmp_image to test SPI transactions
between spi controller and seeprom device
The new qom-tree looks like below.
(qemu) info qom-tree
/machine (powernv10-machine)
/chip[0] (power10_v2.0-pnv-chip)
/pib_spic[0] (pnv-spi)
/pnv-spi-bus.0 (SSI)
/xscom-spi-regs[0] (memory-region)
/pib_spic[1] (pnv-spi)
/pnv-spi-bus.1 (SSI)
/xscom-spi-regs[0] (memory-region)
/pib_spic[2] (pnv-spi)
/pnv-spi-bus.2 (SSI)
/xscom-spi-regs[0] (memory-region)
/pib_spic[3] (pnv-spi)
/pnv-spi-bus.3 (SSI)
/xscom-spi-regs[0] (memory-region)
/pib_spic[4] (pnv-spi)
/pnv-spi-bus.4 (SSI)
/xscom-spi-regs[0] (memory-region)
/pib_spic[5] (pnv-spi)
/pnv-spi-bus.5 (SSI)
/xscom-spi-regs[0] (memory-region)
(qemu) info qom-tree
/machine (powernv10-machine)
/peripheral-anon (container)
/device[0] (25csm04)
/WP#[0] (irq)
/ssi-gpio-cs[0] (irq)
Patches overview in v4.
PATCH1: Create a PNV SPI model and implement configuration unit
to model SCOM registers.
PATCH2: Extend PNV SPI model: implement sequencer FSM and shift engine.
PATCH3: Add Microchip's SEEPROM 25csm04 model on top of m25p80.
PATCH4: Connect SPI controllers to p10 chip and connect cs lines.
PATCH5: Write a qtest pnv-spi-seeprom-test to check the SPI transactions
between spi controller and seeprom device.
Test covered:
make check
make check-avocado
Thank You,
Chalapathi
Chalapathi V (5):
ppc/pnv: Add SPI model
ppc/pnv: Extend SPI model
hw/block: Add Microchip's 25CSM04 to m25p80
hw/ppc: SPI controller wiring to P10 chip
tests/qtest: Add pnv-spi-seeprom qtest
include/hw/ppc/pnv_chip.h | 3 +
include/hw/ppc/pnv_xscom.h | 5 +-
include/hw/ssi/pnv_spi.h | 86 ++
include/hw/ssi/pnv_spi_regs.h | 114 +++
hw/block/m25p80.c | 3 +
hw/ppc/pnv.c | 21 +-
hw/ssi/pnv_spi.c | 1249 ++++++++++++++++++++++++++++
tests/qtest/pnv-spi-seeprom-test.c | 110 +++
hw/ppc/Kconfig | 3 +
hw/ssi/Kconfig | 4 +
hw/ssi/meson.build | 1 +
hw/ssi/trace-events | 21 +
tests/qtest/meson.build | 1 +
13 files changed, 1619 insertions(+), 2 deletions(-)
create mode 100644 include/hw/ssi/pnv_spi.h
create mode 100644 include/hw/ssi/pnv_spi_regs.h
create mode 100644 hw/ssi/pnv_spi.c
create mode 100644 tests/qtest/pnv-spi-seeprom-test.c
--
2.39.3
- [PATCH v4 0/5] hw/ppc: SPI model,
Chalapathi V <=
- [PATCH v4 1/5] ppc/pnv: Add SPI model, Chalapathi V, 2024/06/17
- [PATCH v4 2/5] ppc/pnv: Extend SPI model, Chalapathi V, 2024/06/17
- [PATCH v4 3/5] hw/block: Add Microchip's 25CSM04 to m25p80, Chalapathi V, 2024/06/17
- [PATCH v4 4/5] hw/ppc: SPI controller wiring to P10 chip, Chalapathi V, 2024/06/17
- [PATCH v4 5/5] tests/qtest: Add pnv-spi-seeprom qtest, Chalapathi V, 2024/06/17