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[PULL 03/67] ppc/pnv: Fix LPC serirq routing calculation
From: |
Nicholas Piggin |
Subject: |
[PULL 03/67] ppc/pnv: Fix LPC serirq routing calculation |
Date: |
Mon, 4 Nov 2024 10:17:52 +1000 |
The serirq routing table is split over two registers, the calculation
for the high irqs in the second register did not subtract the irq
offset. This was spotted by Coverity as a shift-by-negative. Fix this
and change the open-coded shifting and masking to use extract32()
function so it's less error-prone.
This went unnoticed because irqs >= 14 are not used in a standard
QEMU/OPAL boot, changing the first QEMU serial-isa irq to 14 to test
does demonstrate serial irqs aren't received, and that this change
fixes that.
Cc: qemu-stable@nongnu.org
Reported-by: Cédric Le Goater <clg@redhat.com>
Resolves: Coverity CID 1558829 (partially)
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/pnv_lpc.c | 10 ++++++++--
target/ppc/cpu.h | 1 +
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index f8aad955b5..80b79dfbbc 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -435,13 +435,19 @@ static void pnv_lpc_eval_serirq_routes(PnvLpcController
*lpc)
return;
}
+ /*
+ * Each of the ISA irqs is routed to one of the 4 SERIRQ irqs with 2
+ * bits, split across 2 OPB registers.
+ */
for (irq = 0; irq <= 13; irq++) {
- int serirq = (lpc->opb_irq_route1 >> (31 - 5 - (irq * 2))) & 0x3;
+ int serirq = extract32(lpc->opb_irq_route1,
+ PPC_BIT32_NR(5 + irq * 2), 2);
lpc->irq_to_serirq_route[irq] = serirq;
}
for (irq = 14; irq < ISA_NUM_IRQS; irq++) {
- int serirq = (lpc->opb_irq_route0 >> (31 - 9 - (irq * 2))) & 0x3;
+ int serirq = extract32(lpc->opb_irq_route0,
+ PPC_BIT32_NR(9 + (irq - 14) * 2), 2);
lpc->irq_to_serirq_route[irq] = serirq;
}
}
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 321ed2da75..bd32a1a5f8 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -40,6 +40,7 @@
#define PPC_BIT_NR(bit) (63 - (bit))
#define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
+#define PPC_BIT32_NR(bit) (31 - (bit))
#define PPC_BIT32(bit) (0x80000000 >> (bit))
#define PPC_BIT8(bit) (0x80 >> (bit))
#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
--
2.45.2
- [PULL 00/67] ppc-for-9.2-1 queue, Nicholas Piggin, 2024/11/03
- [PULL 03/67] ppc/pnv: Fix LPC serirq routing calculation,
Nicholas Piggin <=
- [PULL 04/67] ppc/pnv: Fix LPC POWER8 register sanity check, Nicholas Piggin, 2024/11/03
- [PULL 05/67] target/ppc: Fix mtDPDES targeting SMT siblings, Nicholas Piggin, 2024/11/03
- [PULL 06/67] target/ppc: PMIs are level triggered, Nicholas Piggin, 2024/11/03
- [PULL 07/67] target/ppc: Fix doorbell delivery to threads in powersave, Nicholas Piggin, 2024/11/03
- [PULL 08/67] target/ppc: Fix HFSCR facility checks, Nicholas Piggin, 2024/11/03
- [PULL 09/67] target/ppc: Fix VRMA to not check virtual page class key protection, Nicholas Piggin, 2024/11/03
- [PULL 10/67] ppc/pnv: ADU fix possible buffer overrun with invalid size, Nicholas Piggin, 2024/11/03
- [PULL 11/67] MAINTAINERS: Cover PowerPC SPI model in PowerNV section, Nicholas Piggin, 2024/11/03