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[PATCH v3 2/2] ppc/pnv: Add new PowerPC Special Purpose Registers (RWMR)
From: |
dan tan |
Subject: |
[PATCH v3 2/2] ppc/pnv: Add new PowerPC Special Purpose Registers (RWMR) |
Date: |
Tue, 7 Jan 2025 14:51:02 -0600 |
From: dan tan <dantan@linux.ibm.com>
Register RWMR - Region Weighted Mode Register
for privileged access in Power9 and Power10
It controls what the SPURR register produces.
Specs:
- Power9: https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k
- Power10: https://files.openpower.foundation/s/EgCy7C43p2NSRfR
Signed-off-by: dan tan <dantan@linux.ibm.com>
---
Ver 3 summary:
- change the register to generic read/write from nop/write
Ver 2 summary:
- corrected the previous definition as ITV1
- spec reference:
https://ibm.ent.box.com/s/tmklq90ze7aj8f4n32er1mu3sy9u8k3k (Power9)
- it appears that part of the previous upstream submission SPRs
(SPR_POWER_MMCR3, SPR_POWER_SIER2, SPR_POWER_SIER3) are
already in the current master. Therefore, removed those
from this request.
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_init.c | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 6d074e67dc..fefc741672 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2099,6 +2099,7 @@ void ppc_compat_add_property(Object *obj, const char
*name,
#define SPR_440_INV3 (0x373)
#define SPR_440_ITV0 (0x374)
#define SPR_440_ITV1 (0x375)
+#define SPR_RWMR (0x375)
#define SPR_440_ITV2 (0x376)
#define SPR_440_ITV3 (0x377)
#define SPR_440_CCR1 (0x378)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 7844e16ea5..fd7e001ade 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5773,6 +5773,11 @@ static void register_power9_book4_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_WORT, 0);
+ spr_register_hv(env, SPR_RWMR, "RWMR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
#endif
}
--
2.39.5