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[Qemu-riscv] [PATCH v1 11/27] target/riscv: Add background CSRs accesses
From: |
Alistair Francis |
Subject: |
[Qemu-riscv] [PATCH v1 11/27] target/riscv: Add background CSRs accesses |
Date: |
Fri, 7 Jun 2019 14:55:53 -0700 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu_bits.h | 11 ++++
target/riscv/csr.c | 119 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 130 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index c898bb1102..9c27727e6f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -169,6 +169,17 @@
#define CSR_SPTBR 0x180
#define CSR_SATP 0x180
+/* Background CSRs */
+#define CSR_BSSTATUS 0x200
+#define CSR_BSIE 0x204
+#define CSR_BSTVEC 0x205
+#define CSR_BSSCRATCH 0x240
+#define CSR_BSEPC 0x241
+#define CSR_BSCAUSE 0x242
+#define CSR_BSTVAL 0x243
+#define CSR_BSIP 0x244
+#define CSR_BSATP 0x280
+
/* Physical Memory Protection */
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 911f83ef51..c55eea44ec 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -799,6 +799,115 @@ static int write_hgatp(CPURISCVState *env, int csrno,
target_ulong val)
return 0;
}
+/* Background CSR Registers */
+static int read_bsstatus(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->bsstatus;
+ return 0;
+}
+
+static int write_bsstatus(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->bsstatus = val;
+ return 0;
+}
+
+static int read_bsie(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->bsie;
+ return 0;
+}
+
+static int write_bsie(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->bsie = val;
+ return 0;
+}
+
+static int read_bstvec(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->bstvec;
+ return 0;
+}
+
+static int write_bstvec(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->bstvec = val;
+ return 0;
+}
+
+static int read_bsscratch(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->bsscratch;
+ return 0;
+}
+
+static int write_bsscratch(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->bsscratch = val;
+ return 0;
+}
+
+static int read_bsepc(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->bsepc;
+ return 0;
+}
+
+static int write_bsepc(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->bsepc = val;
+ return 0;
+}
+
+static int read_bscause(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->bscause;
+ return 0;
+}
+
+static int write_bscause(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->bscause = val;
+ return 0;
+}
+
+static int read_bstval(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->bstval;
+ return 0;
+}
+
+static int write_bstval(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->bstval = val;
+ return 0;
+}
+
+static int read_bsip(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = (target_ulong)atomic_read(&env->bsip);
+ return 0;
+}
+
+static int write_bsip(CPURISCVState *env, int csrno, target_ulong val)
+{
+ atomic_set(&env->bsip, val);
+ return 0;
+}
+
+static int read_bsatp(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->bsatp;
+ return 0;
+}
+
+static int write_bsatp(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->bsatp = val;
+ return 0;
+}
+
/* Physical Memory Protection */
static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
{
@@ -987,6 +1096,16 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg
},
[CSR_HGATP] = { hmode, read_hgatp, write_hgatp
},
+ [CSR_BSSTATUS] = { hmode, read_bsstatus, write_bsstatus
},
+ [CSR_BSIE] = { hmode, read_bsie, write_bsie
},
+ [CSR_BSTVEC] = { hmode, read_bstvec, write_bstvec
},
+ [CSR_BSSCRATCH] = { hmode, read_bsscratch, write_bsscratch
},
+ [CSR_BSEPC] = { hmode, read_bsepc, write_bsepc
},
+ [CSR_BSCAUSE] = { hmode, read_bscause, write_bscause
},
+ [CSR_BSTVAL] = { hmode, read_bstval, write_bstval
},
+ [CSR_BSIP] = { hmode, read_bsip, write_bsip
},
+ [CSR_BSATP] = { hmode, read_bsatp, write_bsatp
},
+
/* Physical Memory Protection */
[CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
--
2.21.0
- [Qemu-riscv] [PATCH v1 01/27] target/riscv: Don't set write permissions on dirty PTEs, (continued)
- [Qemu-riscv] [PATCH v1 01/27] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 07/27] target/riscv: Remove strict perm checking for CSR R/W, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 04/27] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 06/27] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 08/27] target/riscv: Create function to test if FP is enabled, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 09/27] target/riscv: Add support for background interrupt setting, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 10/27] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 12/27] target/riscv: Add background register swapping function, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 13/27] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 16/27] riscv: plic: Always set sip.SEIP bit for HS, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 11/27] target/riscv: Add background CSRs accesses,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 15/27] riscv: plic: Remove unused interrupt functions, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 17/27] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 18/27] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 14/27] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 19/27] target/riscv: Add hfence instructions, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 22/27] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 21/27] target/riscv: Mark both sstatus and bsstatus as dirty, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 23/27] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 25/27] target/riscv: Implement second stage MMU, Alistair Francis, 2019/06/07
- [Qemu-riscv] [PATCH v1 24/27] target/riscv: Allow specifying number of MMU stages, Alistair Francis, 2019/06/07