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Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: sifive_test: Add reset func
From: |
Bin Meng |
Subject: |
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: sifive_test: Add reset functionality |
Date: |
Wed, 19 Jun 2019 21:42:21 +0800 |
Hi Alistair,
On Tue, Jun 18, 2019 at 1:15 AM Alistair Francis <address@hidden> wrote:
>
> On Fri, Jun 14, 2019 at 8:30 AM Bin Meng <address@hidden> wrote:
> >
> > This adds a reset opcode for sifive_test device to trigger a system
> > reset for testing purpose.
> >
> > Signed-off-by: Bin Meng <address@hidden>
> > ---
> >
> > hw/riscv/sifive_test.c | 4 ++++
> > include/hw/riscv/sifive_test.h | 3 ++-
> > 2 files changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
> > index 24a04d7..cd86831 100644
> > --- a/hw/riscv/sifive_test.c
> > +++ b/hw/riscv/sifive_test.c
> > @@ -21,6 +21,7 @@
> > #include "qemu/osdep.h"
> > #include "hw/sysbus.h"
> > #include "qemu/module.h"
> > +#include "sysemu/sysemu.h"
> > #include "target/riscv/cpu.h"
> > #include "hw/riscv/sifive_test.h"
> >
> > @@ -40,6 +41,9 @@ static void sifive_test_write(void *opaque, hwaddr addr,
> > exit(code);
> > case FINISHER_PASS:
> > exit(0);
> > + case FINISHER_RESET:
> > + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> > + return;
> > default:
> > break;
> > }
> > diff --git a/include/hw/riscv/sifive_test.h b/include/hw/riscv/sifive_test.h
> > index 71d4c9f..c186a31 100644
> > --- a/include/hw/riscv/sifive_test.h
> > +++ b/include/hw/riscv/sifive_test.h
> > @@ -34,7 +34,8 @@ typedef struct SiFiveTestState {
> >
> > enum {
> > FINISHER_FAIL = 0x3333,
> > - FINISHER_PASS = 0x5555
> > + FINISHER_PASS = 0x5555,
> > + FINISHER_RESET = 0x7777
>
> Do you mind sharing where you got this value from? I can't find
> details on this device in the SiFive manuals.
>
I don't think this is a device that actually exists on SiFive's
chipset. It's hypothetical.
Regards,
Bin