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[Qemu-riscv] [PULL 24/34] RISC-V: Update syscall list for 32-bit support
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 24/34] RISC-V: Update syscall list for 32-bit support. |
Date: |
Fri, 28 Jun 2019 10:32:17 -0700 |
From: Jim Wilson <address@hidden>
32-bit RISC-V uses _llseek instead of lseek as syscall number 62.
Update syscall list from open-embedded build, primarily because
32-bit RISC-V requires statx support.
Tested with cross gcc testsuite runs for rv32 and rv64, with the
pending statx patch also applied.
Signed-off-by: Jim Wilson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
linux-user/riscv/syscall_nr.h | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/linux-user/riscv/syscall_nr.h b/linux-user/riscv/syscall_nr.h
index dab6509e3ade..5c8728220994 100644
--- a/linux-user/riscv/syscall_nr.h
+++ b/linux-user/riscv/syscall_nr.h
@@ -72,7 +72,11 @@
#define TARGET_NR_pipe2 59
#define TARGET_NR_quotactl 60
#define TARGET_NR_getdents64 61
+#ifdef TARGET_RISCV32
+#define TARGET_NR__llseek 62
+#else
#define TARGET_NR_lseek 62
+#endif
#define TARGET_NR_read 63
#define TARGET_NR_write 64
#define TARGET_NR_readv 65
@@ -286,7 +290,16 @@
#define TARGET_NR_membarrier 283
#define TARGET_NR_mlock2 284
#define TARGET_NR_copy_file_range 285
+#define TARGET_NR_preadv2 286
+#define TARGET_NR_pwritev2 287
+#define TARGET_NR_pkey_mprotect 288
+#define TARGET_NR_pkey_alloc 289
+#define TARGET_NR_pkey_free 290
+#define TARGET_NR_statx 291
+#define TARGET_NR_io_pgetevents 292
+#define TARGET_NR_rseq 293
+#define TARGET_NR_kexec_file_load 294
-#define TARGET_NR_syscalls (TARGET_NR_copy_file_range + 1)
+#define TARGET_NR_syscalls (TARGET_NR_kexec_file_load + 1)
#endif
--
2.21.0
- [Qemu-riscv] [PULL 15/34] target/riscv: Add the mcountinhibit CSR, (continued)
- [Qemu-riscv] [PULL 15/34] target/riscv: Add the mcountinhibit CSR, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 13/34] target/riscv: Restructure deprecatd CPUs, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 21/34] RISC-V: Add support for the Zifencei extension, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 19/34] target/riscv: Remove user version information, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 08/34] RISC-V: Check PMP during Page Table Walks, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 17/34] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 18/34] target/riscv: Require either I or E base extension, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 16/34] target/riscv: Set privledge spec 1.11.0 as default, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 22/34] RISC-V: Add support for the Zicsr extension, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 24/34] RISC-V: Update syscall list for 32-bit support.,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 26/34] disas/riscv: Disassemble reserved compressed encodings as illegal, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 20/34] target/riscv: Add support for disabling/enabling Counters, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 23/34] RISC-V: Clear load reservations on context switch and SC, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 25/34] riscv: virt: Add cpu-topology DT node., Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 28/34] riscv: sifive_u: Do not create hard-coded phandles in DT, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 27/34] disas/riscv: Fix `rdinstreth` constraint, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 29/34] riscv: sifive_u: Update the plic hart config to support multicore, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 32/34] hw/riscv: Extend the kernel loading support, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 30/34] hw/riscv: Split out the boot functions, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 31/34] hw/riscv: Add support for loading a firmware, Palmer Dabbelt, 2019/06/28