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[Qemu-riscv] [PULL 31/32] hw/riscv: Add support for loading a firmware
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 31/32] hw/riscv: Add support for loading a firmware |
Date: |
Wed, 3 Jul 2019 01:40:47 -0700 |
From: Alistair Francis <address@hidden>
Add support for loading a firmware file for the virt machine and the
SiFive U. This can be run with the following command:
qemu-system-riscv64 -machine virt -bios fw_jump.bin -kernel vmlinux
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/boot.c | 26 ++++++++++++++++++++++++++
hw/riscv/sifive_u.c | 4 ++++
hw/riscv/virt.c | 4 ++++
include/hw/riscv/boot.h | 2 ++
4 files changed, 36 insertions(+)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 0c8e72e455d7..883df49a0c65 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -23,8 +23,34 @@
#include "exec/cpu-defs.h"
#include "hw/loader.h"
#include "hw/riscv/boot.h"
+#include "hw/boards.h"
#include "elf.h"
+#if defined(TARGET_RISCV32)
+# define KERNEL_BOOT_ADDRESS 0x80400000
+#else
+# define KERNEL_BOOT_ADDRESS 0x80200000
+#endif
+
+target_ulong riscv_load_firmware(const char *firmware_filename,
+ hwaddr firmware_load_addr)
+{
+ uint64_t firmware_entry, firmware_start, firmware_end;
+
+ if (load_elf(firmware_filename, NULL, NULL, NULL, &firmware_entry,
+ &firmware_start, &firmware_end, 0, EM_RISCV, 1, 0) > 0) {
+ return firmware_entry;
+ }
+
+ if (load_image_targphys_as(firmware_filename, firmware_load_addr,
+ ram_size, NULL) > 0) {
+ return firmware_load_addr;
+ }
+
+ error_report("could not load firmware '%s'", firmware_filename);
+ exit(1);
+}
+
target_ulong riscv_load_kernel(const char *kernel_filename)
{
uint64_t kernel_entry, kernel_high;
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f6b9c12e6094..420867155293 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -269,6 +269,10 @@ static void riscv_sifive_u_init(MachineState *machine)
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
+ if (machine->firmware) {
+ riscv_load_firmware(machine->firmware, memmap[SIFIVE_U_DRAM].base);
+ }
+
if (machine->kernel_filename) {
riscv_load_kernel(machine->kernel_filename);
}
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 485aefa99523..d8181a4ff18a 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -398,6 +398,10 @@ static void riscv_virt_board_init(MachineState *machine)
memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
mask_rom);
+ if (machine->firmware) {
+ riscv_load_firmware(machine->firmware, memmap[VIRT_DRAM].base);
+ }
+
if (machine->kernel_filename) {
uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index f84fd6c2df5e..daa179b600f4 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -20,6 +20,8 @@
#ifndef RISCV_BOOT_H
#define RISCV_BOOT_H
+target_ulong riscv_load_firmware(const char *firmware_filename,
+ hwaddr firmware_load_addr);
target_ulong riscv_load_kernel(const char *kernel_filename);
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
uint64_t kernel_entry, hwaddr *start);
--
2.21.0
- [Qemu-riscv] [PULL 16/32] target/riscv: Set privledge spec 1.11.0 as default, (continued)
- [Qemu-riscv] [PULL 16/32] target/riscv: Set privledge spec 1.11.0 as default, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 18/32] target/riscv: Require either I or E base extension, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 20/32] target/riscv: Add support for disabling/enabling Counters, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 24/32] RISC-V: Update syscall list for 32-bit support., Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 19/32] target/riscv: Remove user version information, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 21/32] RISC-V: Add support for the Zifencei extension, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 23/32] RISC-V: Clear load reservations on context switch and SC, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 28/32] riscv: sifive_u: Do not create hard-coded phandles in DT, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 32/32] hw/riscv: Extend the kernel loading support, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 26/32] disas/riscv: Disassemble reserved compressed encodings as illegal, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 31/32] hw/riscv: Add support for loading a firmware,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 25/32] riscv: virt: Add cpu-topology DT node., Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 29/32] riscv: sifive_u: Update the plic hart config to support multicore, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 27/32] disas/riscv: Fix `rdinstreth` constraint, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 30/32] hw/riscv: Split out the boot functions, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 22/32] RISC-V: Add support for the Zicsr extension, Palmer Dabbelt, 2019/07/03
- Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v3, Peter Maydell, 2019/07/04