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[PATCH v3 4/7] riscv/sifive_u: Add the start-in-flash property
From: |
Alistair Francis |
Subject: |
[PATCH v3 4/7] riscv/sifive_u: Add the start-in-flash property |
Date: |
Tue, 8 Oct 2019 16:32:18 -0700 |
Add a property that when set to true QEMU will jump from the ROM code to
the start of flash memory instead of DRAM which is the default
behaviour.
Signed-off-by: Alistair Francis <address@hidden>
---
v3:
- Use the start_addr variable instead of editing reset vector
- Fix function names
hw/riscv/sifive_u.c | 30 +++++++++++++++++++++++++++++-
include/hw/riscv/sifive_u.h | 2 ++
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f5741e9a38..43e9f744a3 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -314,6 +314,7 @@ static void riscv_sifive_u_init(MachineState *machine)
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
+ target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
int i;
/* Initialize SoC */
@@ -356,6 +357,10 @@ static void riscv_sifive_u_init(MachineState *machine)
}
}
+ if (s->start_in_flash) {
+ start_addr = memmap[SIFIVE_U_FLASH0].base;
+ }
+
/* reset vector */
uint32_t reset_vec[8] = {
0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
@@ -368,7 +373,7 @@ static void riscv_sifive_u_init(MachineState *machine)
#endif
0x00028067, /* jr t0 */
0x00000000,
- memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */
+ start_addr, /* start: .dword */
0x00000000,
/* dtb: */
};
@@ -432,8 +437,31 @@ static void riscv_sifive_u_soc_init(Object *obj)
TYPE_CADENCE_GEM);
}
+static bool sifive_u_get_start_in_flash(Object *obj, Error **errp)
+{
+ SiFiveUState *s = RISCV_U_MACHINE(obj);
+
+ return s->start_in_flash;
+}
+
+static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **errp)
+{
+ SiFiveUState *s = RISCV_U_MACHINE(obj);
+
+ s->start_in_flash = value;
+}
+
static void riscv_sifive_u_machine_instance_init(Object *obj)
{
+ SiFiveUState *s = RISCV_U_MACHINE(obj);
+
+ s->start_in_flash = false;
+ object_property_add_bool(obj, "start-in-flash",
sifive_u_get_start_in_flash,
+ sifive_u_set_start_in_flash, NULL);
+ object_property_set_description(obj, "start-in-flash",
+ "Set on to tell QEMU's ROM to jump to " \
+ "flash. Otherwise QEMU will jump to DRAM",
+ NULL);
}
static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index a921079fbe..2656b43c58 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -57,6 +57,8 @@ typedef struct SiFiveUState {
void *fdt;
int fdt_size;
+
+ bool start_in_flash;
} SiFiveUState;
enum {
--
2.23.0
- [PATCH v3 0/7] RISC-V: Add more machine memory, Alistair Francis, 2019/10/08
- [PATCH v3 1/7] riscv/sifive_u: Add L2-LIM cache memory, Alistair Francis, 2019/10/08
- [PATCH v3 2/7] riscv/sifive_u: Add QSPI memory region, Alistair Francis, 2019/10/08
- [PATCH v3 3/7] riscv/sifive_u: Manually define the machine, Alistair Francis, 2019/10/08
- [PATCH v3 4/7] riscv/sifive_u: Add the start-in-flash property,
Alistair Francis <=
- [PATCH v3 5/7] riscv/virt: Manually define the machine, Alistair Francis, 2019/10/08
- [PATCH v3 6/7] riscv/virt: Add the PFlash CFI01 device, Alistair Francis, 2019/10/08
- [PATCH v3 7/7] riscv/virt: Jump to pflash if specified, Alistair Francis, 2019/10/08