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[PATCH v2 06/27] target/riscv: Add the Hypervisor CSRs to CPUState
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From: |
Alistair Francis |
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Subject: |
[PATCH v2 06/27] target/riscv: Add the Hypervisor CSRs to CPUState |
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Date: |
Fri, 25 Oct 2019 16:23:28 -0700 |
As the MIP CSR is 32-bits to allow atomic_read on 32-bit hosts the vsip
is 32-bit as well.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Chih-Min Chao <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bb7a0e27a7..a1625e8af0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -145,6 +145,23 @@ struct CPURISCVState {
target_ulong mcause;
target_ulong mtval; /* since: priv-1.10.0 */
+ /* Hypervisor CSRs */
+ target_ulong hstatus;
+ target_ulong hedeleg;
+ target_ulong hideleg;
+ target_ulong hgatp;
+
+ /* Virtual CSRs */
+ target_ulong vsstatus;
+ uint32_t vsip;
+ target_ulong vsie;
+ target_ulong vstvec;
+ target_ulong vsscratch;
+ target_ulong vsepc;
+ target_ulong vscause;
+ target_ulong vstval;
+ target_ulong vsatp;
+
target_ulong scounteren;
target_ulong mcounteren;
--
2.23.0
- [PATCH v2 00/27] Add RISC-V Hypervisor Extension v0.4, Alistair Francis, 2019/10/25
- [PATCH v2 01/27] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/10/25
- [PATCH v2 02/27] target/riscv: Add the Hypervisor extension, Alistair Francis, 2019/10/25
- [PATCH v2 03/27] target/riscv: Add the virtulisation mode, Alistair Francis, 2019/10/25
- [PATCH v2 04/27] target/riscv: Add the force HS exception mode, Alistair Francis, 2019/10/25
- [PATCH v2 08/27] target/riscv: Dump Hypervisor registers if enabled, Alistair Francis, 2019/10/25
- [PATCH v2 06/27] target/riscv: Add the Hypervisor CSRs to CPUState,
Alistair Francis <=
- [PATCH v2 07/27] target/riscv: Print priv and virt in disas log, Alistair Francis, 2019/10/25
- [PATCH v2 05/27] target/riscv: Fix CSR perm checking for HS mode, Alistair Francis, 2019/10/25
- [PATCH v2 10/27] target/riscv: Add Hypervisor virtual CSRs accesses, Alistair Francis, 2019/10/25
- [PATCH v2 09/27] target/riscv: Add Hypervisor CSR access functions, Alistair Francis, 2019/10/25
- [PATCH v2 11/27] target/riscv: Convert mie and mstatus to pointers, Alistair Francis, 2019/10/25
- [PATCH v2 17/27] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/10/25
- [PATCH v2 18/27] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/10/25
- [PATCH v2 20/27] target/riscv: Disable guest FP support based on virtual status, Alistair Francis, 2019/10/25
- [PATCH v2 19/27] target/riscv: Add hfence instructions, Alistair Francis, 2019/10/25
- [PATCH v2 22/27] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2019/10/25