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[PULL 07/18] riscv/sifive_u: Add L2-LIM cache memory
From: |
Palmer Dabbelt |
Subject: |
[PULL 07/18] riscv/sifive_u: Add L2-LIM cache memory |
Date: |
Mon, 28 Oct 2019 08:48:51 -0700 |
From: Alistair Francis <address@hidden>
On reset only a single L2 cache way is enabled, the others are exposed
as memory that can be used by early boot firmware. This L2 region is
generally disabled using the WayEnable register at a later stage in the
boot process. To allow firmware to target QEMU and the HiFive Unleashed
let's add the L2 LIM (LooselyIntegrated Memory).
Ideally we would want to adjust the size of this chunk of memory as the
L2 Cache Controller WayEnable register is incremented. Unfortunately I
don't see a nice way to handle reducing or blocking out the L2 LIM while
still allowing it be re returned to all enabled from a reset.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_u.c | 16 ++++++++++++++++
include/hw/riscv/sifive_u.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 1ac51e3632..fbaa3a234e 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -65,6 +65,7 @@ static const struct MemmapEntry {
[SIFIVE_U_DEBUG] = { 0x0, 0x100 },
[SIFIVE_U_MROM] = { 0x1000, 0x11000 },
[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
+ [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
[SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
[SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
@@ -432,6 +433,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev,
Error **errp)
const struct MemmapEntry *memmap = sifive_u_memmap;
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
+ MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
char *plic_hart_config;
size_t plic_hart_config_len;
@@ -460,6 +462,20 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev,
Error **errp)
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
mask_rom);
+ /*
+ * Add L2-LIM at reset size.
+ * This should be reduced in size as the L2 Cache Controller WayEnable
+ * register is incremented. Unfortunately I don't see a nice (or any) way
+ * to handle reducing or blocking out the L2 LIM while still allowing it
+ * be re returned to all enabled after a reset. For the time being, just
+ * leave it enabled all the time. This won't break anything, but will be
+ * too generous to misbehaving guests.
+ */
+ memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
+ memmap[SIFIVE_U_L2LIM].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base,
+ l2lim_mem);
+
/* create PLIC hart topology configuration string */
plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) *
ms->smp.cpus;
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 4850805ee7..66ee76a780 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -58,6 +58,7 @@ enum {
SIFIVE_U_DEBUG,
SIFIVE_U_MROM,
SIFIVE_U_CLINT,
+ SIFIVE_U_L2LIM,
SIFIVE_U_PLIC,
SIFIVE_U_PRCI,
SIFIVE_U_UART0,
--
2.21.0
- [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2, Palmer Dabbelt, 2019/10/28
- [PULL 01/18] riscv: Skip checking CSR privilege level in debugger mode, Palmer Dabbelt, 2019/10/28
- [PULL 02/18] RISC-V: Handle bus errors in the page table walker, Palmer Dabbelt, 2019/10/28
- [PULL 03/18] RISC-V: Implement cpu_do_transaction_failed, Palmer Dabbelt, 2019/10/28
- [PULL 05/18] riscv: sifive_u: Add ethernet0 to the aliases node, Palmer Dabbelt, 2019/10/28
- [PULL 06/18] linux-user/riscv: Propagate fault address, Palmer Dabbelt, 2019/10/28
- [PULL 04/18] riscv: hw: Drop "clock-frequency" property of cpu nodes, Palmer Dabbelt, 2019/10/28
- [PULL 07/18] riscv/sifive_u: Add L2-LIM cache memory,
Palmer Dabbelt <=
- [PULL 08/18] riscv/sifive_u: Add QSPI memory region, Palmer Dabbelt, 2019/10/28
- [PULL 09/18] riscv/sifive_u: Manually define the machine, Palmer Dabbelt, 2019/10/28
- [PULL 11/18] riscv/virt: Manually define the machine, Palmer Dabbelt, 2019/10/28
- [PULL 10/18] riscv/sifive_u: Add the start-in-flash property, Palmer Dabbelt, 2019/10/28
- [PULL 12/18] riscv/virt: Add the PFlash CFI01 device, Palmer Dabbelt, 2019/10/28
- [PULL 13/18] riscv/virt: Jump to pflash if specified, Palmer Dabbelt, 2019/10/28
- [PULL 14/18] target/riscv: Tell gdbstub the correct number of CSRs, Palmer Dabbelt, 2019/10/28
- [PULL 16/18] target/riscv: Make the priv register writable by GDB, Palmer Dabbelt, 2019/10/28
- [PULL 15/18] target/riscv: Expose "priv" register for GDB for reads, Palmer Dabbelt, 2019/10/28
- [PULL 17/18] riscv/boot: Fix possible memory leak, Palmer Dabbelt, 2019/10/28