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[PULL 13/38] target/riscv: Add Hypervisor machine CSRs accesses
From: |
Palmer Dabbelt |
Subject: |
[PULL 13/38] target/riscv: Add Hypervisor machine CSRs accesses |
Date: |
Mon, 2 Mar 2020 16:48:23 -0800 |
From: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/csr.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 3fa8d2cfda..f7333286bd 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -984,6 +984,30 @@ static int write_vsatp(CPURISCVState *env, int csrno,
target_ulong val)
return 0;
}
+static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->mtval2;
+ return 0;
+}
+
+static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->mtval2 = val;
+ return 0;
+}
+
+static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ *val = env->mtinst;
+ return 0;
+}
+
+static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val)
+{
+ env->mtinst = val;
+ return 0;
+}
+
/* Physical Memory Protection */
static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
{
@@ -1207,6 +1231,9 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_VSTVAL] = { hmode, read_vstval, write_vstval
},
[CSR_VSATP] = { hmode, read_vsatp, write_vsatp
},
+ [CSR_MTVAL2] = { hmode, read_mtval2, write_mtval2
},
+ [CSR_MTINST] = { hmode, read_mtinst, write_mtinst
},
+
/* Physical Memory Protection */
[CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
--
2.25.0.265.gbab2e86ba0-goog
- [PULL 21/38] target/riscv: Add hypvervisor trap support, (continued)
- [PULL 21/38] target/riscv: Add hypvervisor trap support, Palmer Dabbelt, 2020/03/02
- [PULL 04/38] target/riscv: Add support for the new execption numbers, Palmer Dabbelt, 2020/03/02
- [PULL 15/38] target/riscv: Set VS bits in mideleg for Hyp extension, Palmer Dabbelt, 2020/03/02
- [PULL 16/38] target/riscv: Extend the MIE CSR to support virtulisation, Palmer Dabbelt, 2020/03/02
- [PULL 10/38] target/riscv: Dump Hypervisor registers if enabled, Palmer Dabbelt, 2020/03/02
- [PULL 12/38] target/riscv: Add Hypervisor virtual CSRs accesses, Palmer Dabbelt, 2020/03/02
- [PULL 18/38] target/riscv: Add support for virtual interrupt setting, Palmer Dabbelt, 2020/03/02
- [PULL 13/38] target/riscv: Add Hypervisor machine CSRs accesses,
Palmer Dabbelt <=
- [PULL 22/38] target/riscv: Add Hypervisor trap return support, Palmer Dabbelt, 2020/03/02
- [PULL 31/38] target/riscv: Raise the new execptions when 2nd stage translation fails, Palmer Dabbelt, 2020/03/02
- [PULL 30/38] target/riscv: Implement second stage MMU, Palmer Dabbelt, 2020/03/02
- [PULL 19/38] target/ricsv: Flush the TLB on virtulisation mode changes, Palmer Dabbelt, 2020/03/02
- [PULL 23/38] target/riscv: Add hfence instructions, Palmer Dabbelt, 2020/03/02
- [PULL 20/38] target/riscv: Generate illegal instruction on WFI when V=1, Palmer Dabbelt, 2020/03/02
- [PULL 24/38] target/riscv: Remove the hret instruction, Palmer Dabbelt, 2020/03/02
- [PULL 33/38] target/riscv: Add support for the 32-bit MSTATUSH CSR, Palmer Dabbelt, 2020/03/02
- [PULL 29/38] target/riscv: Allow specifying MMU stage, Palmer Dabbelt, 2020/03/02
- [PULL 25/38] target/riscv: Only set TB flags with FP status if enabled, Palmer Dabbelt, 2020/03/02