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[PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC
From: |
Alistair Francis |
Subject: |
[PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC |
Date: |
Tue, 3 Mar 2020 17:29:13 -0800 |
At present the board serial number is hard-coded to 1, and passed
to OTP model during initialization. Firmware (FSBL, U-Boot) uses
the serial number to generate a unique MAC address for the on-chip
ethernet controller. When multiple QEMU 'sifive_u' instances are
created and connected to the same subnet, they all have the same
MAC address hence it creates a unusable network.
A new "serial" property is introduced to the sifive_u SoC to specify
the board serial number. When not given, the default serial number
1 is used.
Suggested-by: Bin Meng <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
---
hw/riscv/sifive_u.c | 8 +++++++-
include/hw/riscv/sifive_u.h | 2 ++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 9a0145b5b4..e52f9d0bd4 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -488,7 +488,7 @@ static void riscv_sifive_u_soc_init(Object *obj)
TYPE_SIFIVE_U_PRCI);
sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp),
TYPE_SIFIVE_U_OTP);
- qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL);
+ qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
TYPE_CADENCE_GEM);
}
@@ -607,10 +607,16 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev,
Error **errp)
memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
}
+static Property riscv_sifive_u_soc_props[] = {
+ DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
+ DEFINE_PROP_END_OF_LIST()
+};
+
static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
+ device_class_set_props(dc, riscv_sifive_u_soc_props);
dc->realize = riscv_sifive_u_soc_realize;
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
dc->user_creatable = false;
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 82667b5746..a2baa1de5f 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -42,6 +42,8 @@ typedef struct SiFiveUSoCState {
SiFiveUPRCIState prci;
SiFiveUOTPState otp;
CadenceGEMState gem;
+
+ uint32_t serial;
} SiFiveUSoCState;
#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u")
--
2.25.1
- [PATCH v1 0/3] hw/riscv: Add a serial property to the sifive_u machine, Alistair Francis, 2020/03/03
- [PATCH v1 1/3] riscv/sifive_u: Fix up file ordering, Alistair Francis, 2020/03/03
- [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC,
Alistair Francis <=
- Re: [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC, Bin Meng, 2020/03/04
- Re: [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC, Alistair Francis, 2020/03/04
- Re: [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC, Bin Meng, 2020/03/05
- Re: [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC, Alistair Francis, 2020/03/05
- Re: [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC, Bin Meng, 2020/03/05
- Re: [PATCH v1 2/3] riscv/sifive_u: Add a serial property to the sifive_u SoC, Alistair Francis, 2020/03/06
[PATCH v1 3/3] riscv/sifive_u: Add a serial property to the sifive_u machine, Alistair Francis, 2020/03/03