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[PATCH v3 01/60] target/riscv: add vector extension field in CPURISCVSta
From: |
LIU Zhiwei |
Subject: |
[PATCH v3 01/60] target/riscv: add vector extension field in CPURISCVState |
Date: |
Mon, 9 Mar 2020 16:19:43 +0800 |
The 32 vector registers will be viewed as a continuous memory block.
It avoids the convension between element index and (regno, offset).
Thus elements can be directly accessed by offset from the first vector
base address.
Signed-off-by: LIU Zhiwei <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/riscv/cpu.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3dcdf92227..0c1f7bdd8b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -64,6 +64,7 @@
#define RVA RV('A')
#define RVF RV('F')
#define RVD RV('D')
+#define RVV RV('V')
#define RVC RV('C')
#define RVS RV('S')
#define RVU RV('U')
@@ -94,9 +95,20 @@ typedef struct CPURISCVState CPURISCVState;
#include "pmp.h"
+#define RV_VLEN_MAX 512
+
struct CPURISCVState {
target_ulong gpr[32];
uint64_t fpr[32]; /* assume both F and D extensions */
+
+ /* vector coprocessor state. */
+ uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
+ target_ulong vxrm;
+ target_ulong vxsat;
+ target_ulong vl;
+ target_ulong vstart;
+ target_ulong vtype;
+
target_ulong pc;
target_ulong load_res;
target_ulong load_val;
--
2.23.0
- [PATCH v3 00/60] target/riscv: support vector extension v0.7.1, LIU Zhiwei, 2020/03/09
- [PATCH v3 01/60] target/riscv: add vector extension field in CPURISCVState,
LIU Zhiwei <=
- [PATCH v3 02/60] target/riscv: implementation-defined constant parameters, LIU Zhiwei, 2020/03/09
- [PATCH v3 03/60] target/riscv: support vector extension csr, LIU Zhiwei, 2020/03/09
- [PATCH v3 07/60] target/riscv: add fault-only-first unit stride load, LIU Zhiwei, 2020/03/09
- [PATCH v3 06/60] target/riscv: add vector index load and store instructions, LIU Zhiwei, 2020/03/09
- [PATCH v3 04/60] target/riscv: add vector configure instruction, LIU Zhiwei, 2020/03/09
- [PATCH v3 09/60] target/riscv: vector single-width integer add and subtract, LIU Zhiwei, 2020/03/09
- [PATCH v3 10/60] target/riscv: vector widening integer add and subtract, LIU Zhiwei, 2020/03/09
- [PATCH v3 05/60] target/riscv: add vector stride load and store instructions, LIU Zhiwei, 2020/03/09
- [PATCH v3 08/60] target/riscv: add vector amo operations, LIU Zhiwei, 2020/03/09
- [PATCH v3 12/60] target/riscv: vector bitwise logical instructions, LIU Zhiwei, 2020/03/09