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Re: [PATCH v5 05/60] target/riscv: add vector stride load and store inst
From: |
Richard Henderson |
Subject: |
Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions |
Date: |
Fri, 13 Mar 2020 18:36:01 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> Vector strided operations access the first memory element at the base address,
> and then access subsequent elements at address increments given by the byte
> offset contained in the x register specified by rs2.
>
> Vector unit-stride operations access elements stored contiguously in memory
> starting from the base effective address. It can been seen as a special
> case of strided operations.
>
> Signed-off-by: LIU Zhiwei <address@hidden>
> ---
> target/riscv/cpu.h | 6 +
> target/riscv/helper.h | 105 ++++++
> target/riscv/insn32.decode | 32 ++
> target/riscv/insn_trans/trans_rvv.inc.c | 340 ++++++++++++++++++++
> target/riscv/translate.c | 7 +
> target/riscv/vector_helper.c | 406 ++++++++++++++++++++++++
> 6 files changed, 896 insertions(+)
With the changes for has_ext,
Reviewed-by: Richard Henderson <address@hidden>
r~
- Re: [PATCH v5 04/60] target/riscv: add vector configure instruction, (continued)
Re: [PATCH v5 05/60] target/riscv: add vector stride load and store instructions,
Richard Henderson <=
[PATCH v5 06/60] target/riscv: add vector index load and store instructions, LIU Zhiwei, 2020/03/12
[PATCH v5 07/60] target/riscv: add fault-only-first unit stride load, LIU Zhiwei, 2020/03/12
[PATCH v5 08/60] target/riscv: add vector amo operations, LIU Zhiwei, 2020/03/12