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Re: [PATCH v5 17/60] target/riscv: vector single-width integer multiply
From: |
Richard Henderson |
Subject: |
Re: [PATCH v5 17/60] target/riscv: vector single-width integer multiply instructions |
Date: |
Fri, 13 Mar 2020 23:52:51 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +static int64_t do_mulhsu_d(int64_t s2, uint64_t s1)
> +{
> + uint64_t hi_64, lo_64, abs_s2 = s2;
> +
> + if (s2 < 0) {
> + abs_s2 = -s2;
> + }
> + mulu64(&lo_64, &hi_64, abs_s2, s1);
> + if ((int64_t)(s2 ^ s1) < 0) {
Why would the sign of s1 be relevant?
It's always unsigned.
We have code for this in e.g. tcg_gen_mulsu2_i64
mulu4(&lo, &hi, s1, s2);
if ((int64_t)s2 < 0) {
hi -= s2;
}
r~
- Re: [PATCH v5 12/60] target/riscv: vector bitwise logical instructions, (continued)
- [PATCH v5 13/60] target/riscv: vector single-width bit shift instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 14/60] target/riscv: vector narrowing integer right shift instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 15/60] target/riscv: vector integer comparison instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 16/60] target/riscv: vector integer min/max instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 17/60] target/riscv: vector single-width integer multiply instructions, LIU Zhiwei, 2020/03/12
- Re: [PATCH v5 17/60] target/riscv: vector single-width integer multiply instructions,
Richard Henderson <=
- [PATCH v5 18/60] target/riscv: vector integer divide instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 19/60] target/riscv: vector widening integer multiply instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 20/60] target/riscv: vector single-width integer multiply-add instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 21/60] target/riscv: vector widening integer multiply-add instructions, LIU Zhiwei, 2020/03/12
- [PATCH v5 22/60] target/riscv: vector integer merge and move instructions, LIU Zhiwei, 2020/03/12