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[PATCH v6 56/61] target/riscv: integer scalar move instruction
From: |
LIU Zhiwei |
Subject: |
[PATCH v6 56/61] target/riscv: integer scalar move instruction |
Date: |
Tue, 17 Mar 2020 23:06:48 +0800 |
Signed-off-by: LIU Zhiwei <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/riscv/helper.h | 5 +++++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 26 +++++++++++++++++++++++++
target/riscv/vector_helper.c | 18 +++++++++++++++++
4 files changed, 50 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 3d0e2e72bd..2e3bfdf1dc 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1109,3 +1109,8 @@ DEF_HELPER_4(vid_v_b, void, ptr, ptr, env, i32)
DEF_HELPER_4(vid_v_h, void, ptr, ptr, env, i32)
DEF_HELPER_4(vid_v_w, void, ptr, ptr, env, i32)
DEF_HELPER_4(vid_v_d, void, ptr, ptr, env, i32)
+
+DEF_HELPER_3(vmv_s_x_b, void, ptr, tl, env)
+DEF_HELPER_3(vmv_s_x_h, void, ptr, tl, env)
+DEF_HELPER_3(vmv_s_x_w, void, ptr, tl, env)
+DEF_HELPER_3(vmv_s_x_d, void, ptr, tl, env)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 26dd0f1b1b..0741a25540 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -562,6 +562,7 @@ vmsof_m 010110 . ..... 00010 010 ..... 1010111
@r2_vm
viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
+vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 4d7bb6b54e..4cf4e54d12 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2438,3 +2438,29 @@ static bool trans_vext_x_v(DisasContext *s, arg_r *a)
tcg_temp_free(dest);
return true;
}
+
+/* Integer Scalar Move Instruction */
+typedef void gen_helper_vmv_s_x(TCGv_ptr, TCGv, TCGv_env);
+static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
+{
+ if (vext_check_isa_ill(s)) {
+ TCGv_ptr dest;
+ TCGv src1;
+ static gen_helper_vmv_s_x * const fns[4] = {
+ gen_helper_vmv_s_x_b, gen_helper_vmv_s_x_h,
+ gen_helper_vmv_s_x_w, gen_helper_vmv_s_x_d
+ };
+
+ src1 = tcg_temp_new();
+ dest = tcg_temp_new_ptr();
+ gen_get_gpr(src1, a->rs1);
+ tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
+
+ fns[s->sew](dest, src1, cpu_env);
+
+ tcg_temp_free(src1);
+ tcg_temp_free_ptr(dest);
+ return true;
+ }
+ return false;
+}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 769894c5be..7f67a283c9 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4673,3 +4673,21 @@ GEN_VEXT_VID_V(vid_v_b, uint8_t, H1, clearb)
GEN_VEXT_VID_V(vid_v_h, uint16_t, H2, clearh)
GEN_VEXT_VID_V(vid_v_w, uint32_t, H4, clearl)
GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq)
+
+/*
+ *** Vector Permutation Instructions
+ */
+/* Integer Scalar Move Instruction */
+#define GEN_VEXT_VMV_S_X(NAME, ETYPE, H, CLEAR_FN) \
+void HELPER(NAME)(void *vd, target_ulong s1, CPURISCVState *env) \
+{ \
+ if (env->vl == 0) { \
+ return; \
+ } \
+ *((ETYPE *)vd + H(0)) = s1; \
+ CLEAR_FN(vd, 1, sizeof(ETYPE), env_archcpu(env)->cfg.vlen / 8); \
+}
+GEN_VEXT_VMV_S_X(vmv_s_x_b, uint8_t, H1, clearb)
+GEN_VEXT_VMV_S_X(vmv_s_x_h, uint16_t, H2, clearh)
+GEN_VEXT_VMV_S_X(vmv_s_x_w, uint32_t, H4, clearl)
+GEN_VEXT_VMV_S_X(vmv_s_x_d, uint64_t, H8, clearq)
--
2.23.0
- [PATCH v6 48/61] target/riscv: vector widening floating-point reduction instructions, (continued)
- [PATCH v6 48/61] target/riscv: vector widening floating-point reduction instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 49/61] target/riscv: vector mask-register logical instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 50/61] target/riscv: vector mask population count vmpopc, LIU Zhiwei, 2020/03/17
- [PATCH v6 51/61] target/riscv: vmfirst find-first-set mask bit, LIU Zhiwei, 2020/03/17
- [PATCH v6 52/61] target/riscv: set-X-first mask bit, LIU Zhiwei, 2020/03/17
- [PATCH v6 53/61] target/riscv: vector iota instruction, LIU Zhiwei, 2020/03/17
- [PATCH v6 54/61] target/riscv: vector element index instruction, LIU Zhiwei, 2020/03/17
- [PATCH v6 55/61] target/riscv: integer extract instruction, LIU Zhiwei, 2020/03/17
- [PATCH v6 56/61] target/riscv: integer scalar move instruction,
LIU Zhiwei <=
- [PATCH v6 57/61] target/riscv: floating-point scalar move instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 58/61] target/riscv: vector slide instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 59/61] target/riscv: vector register gather instruction, LIU Zhiwei, 2020/03/17
- [PATCH v6 60/61] target/riscv: vector compress instruction, LIU Zhiwei, 2020/03/17
- [PATCH v6 61/61] target/riscv: configure and turn on vector extension from command line, LIU Zhiwei, 2020/03/17