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[PATCH v7 56/61] target/riscv: integer scalar move instruction
From: |
LIU Zhiwei |
Subject: |
[PATCH v7 56/61] target/riscv: integer scalar move instruction |
Date: |
Mon, 30 Mar 2020 23:36:28 +0800 |
Signed-off-by: LIU Zhiwei <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 60 +++++++++++++++++++++++++
2 files changed, 61 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 26dd0f1b1b..0741a25540 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -562,6 +562,7 @@ vmsof_m 010110 . ..... 00010 010 ..... 1010111
@r2_vm
viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
+vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 1bd4fa99ff..61c46e4c1c 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2664,3 +2664,63 @@ static bool trans_vext_x_v(DisasContext *s, arg_r *a)
tcg_temp_free_i64(tmp);
return true;
}
+
+/* Integer Scalar Move Instruction */
+
+static void store_element(TCGv_i64 val, TCGv_ptr base,
+ int ofs, int sew)
+{
+ switch (sew) {
+ case MO_8:
+ tcg_gen_st8_i64(val, base, ofs);
+ break;
+ case MO_16:
+ tcg_gen_st16_i64(val, base, ofs);
+ break;
+ case MO_32:
+ tcg_gen_st32_i64(val, base, ofs);
+ break;
+ case MO_64:
+ tcg_gen_st_i64(val, base, ofs);
+ break;
+ default:
+ g_assert_not_reached();
+ break;
+ }
+}
+
+/*
+ * Store vreg[idx] = val.
+ * The index must be in range of VLMAX.
+ */
+static void vec_element_storei(DisasContext *s, int vreg,
+ int idx, TCGv_i64 val)
+{
+ store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew);
+}
+
+/* vmv.s.x vd, rs1 # vd[0] = rs1 */
+static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
+{
+ if (vext_check_isa_ill(s)) {
+ /* This instruction ignores LMUL and vector register groups */
+ int maxsz = s->vlen >> 3;
+ TCGv_i64 t1;
+ TCGLabel *over = gen_new_label();
+
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+ tcg_gen_gvec_dup64i(vreg_ofs(s, a->rd), maxsz, maxsz, 0);
+ if (a->rs1 == 0) {
+ goto done;
+ }
+
+ t1 = tcg_temp_new_i64();
+ tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
+ vec_element_storei(s, a->rd, 0, t1);
+ tcg_temp_free_i64(t1);
+ done:
+ gen_set_label(over);
+ return true;
+ }
+ return false;
+}
--
2.23.0
- [PATCH v7 46/61] target/riscv: vector wideing integer reduction instructions, (continued)
- [PATCH v7 46/61] target/riscv: vector wideing integer reduction instructions, LIU Zhiwei, 2020/03/30
- [PATCH v7 47/61] target/riscv: vector single-width floating-point reduction instructions, LIU Zhiwei, 2020/03/30
- [PATCH v7 48/61] target/riscv: vector widening floating-point reduction instructions, LIU Zhiwei, 2020/03/30
- [PATCH v7 49/61] target/riscv: vector mask-register logical instructions, LIU Zhiwei, 2020/03/30
- [PATCH v7 50/61] target/riscv: vector mask population count vmpopc, LIU Zhiwei, 2020/03/30
- [PATCH v7 51/61] target/riscv: vmfirst find-first-set mask bit, LIU Zhiwei, 2020/03/30
- [PATCH v7 52/61] target/riscv: set-X-first mask bit, LIU Zhiwei, 2020/03/30
- [PATCH v7 53/61] target/riscv: vector iota instruction, LIU Zhiwei, 2020/03/30
- [PATCH v7 54/61] target/riscv: vector element index instruction, LIU Zhiwei, 2020/03/30
- [PATCH v7 55/61] target/riscv: integer extract instruction, LIU Zhiwei, 2020/03/30
- [PATCH v7 56/61] target/riscv: integer scalar move instruction,
LIU Zhiwei <=
- [PATCH v7 57/61] target/riscv: floating-point scalar move instructions, LIU Zhiwei, 2020/03/30
- [PATCH v7 58/61] target/riscv: vector slide instructions, LIU Zhiwei, 2020/03/30
- [PATCH v7 59/61] target/riscv: vector register gather instruction, LIU Zhiwei, 2020/03/30
- [PATCH v7 60/61] target/riscv: vector compress instruction, LIU Zhiwei, 2020/03/30
- [PATCH v7 61/61] target/riscv: configure and turn on vector extension from command line, LIU Zhiwei, 2020/03/30
- Re: [PATCH v7 00/61] target/riscv: support vector extension v0.7.1, no-reply, 2020/03/30