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Re: [PATCH v2 1/2] hw/riscv: Modify MROM size to end at 0x10000
From: |
Alistair Francis |
Subject: |
Re: [PATCH v2 1/2] hw/riscv: Modify MROM size to end at 0x10000 |
Date: |
Thu, 9 Jul 2020 10:19:00 -0700 |
On Thu, Jul 9, 2020 at 3:06 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> At present the size of Mask ROM for sifive_u / spike / virt machines
> is set to 0x11000, which ends at an unusual address. This changes the
> size to 0xf000 so that it ends at 0x10000.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
>
> (no changes since v1)
>
> hw/riscv/sifive_u.c | 2 +-
> hw/riscv/spike.c | 2 +-
> hw/riscv/virt.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index dc46f64..3413369 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -70,7 +70,7 @@ static const struct MemmapEntry {
> hwaddr size;
> } sifive_u_memmap[] = {
> [SIFIVE_U_DEBUG] = { 0x0, 0x100 },
> - [SIFIVE_U_MROM] = { 0x1000, 0x11000 },
> + [SIFIVE_U_MROM] = { 0x1000, 0xf000 },
> [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
> [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
> [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index a187aa3..ea4be98 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -57,7 +57,7 @@ static const struct MemmapEntry {
> hwaddr base;
> hwaddr size;
> } spike_memmap[] = {
> - [SPIKE_MROM] = { 0x1000, 0x11000 },
> + [SPIKE_MROM] = { 0x1000, 0xf000 },
> [SPIKE_CLINT] = { 0x2000000, 0x10000 },
> [SPIKE_DRAM] = { 0x80000000, 0x0 },
> };
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 5ca49c5..37b8c55 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -53,7 +53,7 @@ static const struct MemmapEntry {
> hwaddr size;
> } virt_memmap[] = {
> [VIRT_DEBUG] = { 0x0, 0x100 },
> - [VIRT_MROM] = { 0x1000, 0x11000 },
> + [VIRT_MROM] = { 0x1000, 0xf000 },
> [VIRT_TEST] = { 0x100000, 0x1000 },
> [VIRT_RTC] = { 0x101000, 0x1000 },
> [VIRT_CLINT] = { 0x2000000, 0x10000 },
> --
> 2.7.4
>
>
- [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU, (continued)
- [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU, Bin Meng, 2020/07/09
- Re: [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU, Alistair Francis, 2020/07/09
- Re: [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU, Palmer Dabbelt, 2020/07/09
- Re: [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU, Bin Meng, 2020/07/09
- Re: [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU, Alistair Francis, 2020/07/11
- Re: [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU, Bin Meng, 2020/07/12
- Re: [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU, Alistair Francis, 2020/07/13
- Re: [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU, Bin Meng, 2020/07/09
- Re: [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU, Alistair Francis, 2020/07/11
- Re: [PATCH v2 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU, Bin Meng, 2020/07/12
Re: [PATCH v2 1/2] hw/riscv: Modify MROM size to end at 0x10000,
Alistair Francis <=