[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [RFC 06/65] target/riscv: rvv-0.9: add vcsr register
|
From: |
Richard Henderson |
|
Subject: |
Re: [RFC 06/65] target/riscv: rvv-0.9: add vcsr register |
|
Date: |
Fri, 10 Jul 2020 10:02:28 -0700 |
|
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 |
On 7/10/20 3:48 AM, frank.chang@sifive.com wrote:
> + [CSR_VCSR] = { vs, read_vcsr, write_vcsr
> },
As long as you have the vext_spec argument, you need a separate vs_0_9
predicate function, so that this csr is not available to VEXT_VERSION_0_07_1.
r~
- [RFC 00/65] target/riscv: support vector extension v0.9, frank . chang, 2020/07/10
- [RFC 27/65] target/riscv: rvv-0.9: iota instruction, frank . chang, 2020/07/10
- [RFC 37/65] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions, frank . chang, 2020/07/10
- [RFC 44/65] target/riscv: rvv-0.9: mask-register logical instructions, frank . chang, 2020/07/10
- [RFC 03/65] target/riscv: fix return value of do_opivx_widen(), frank . chang, 2020/07/10
- [RFC 06/65] target/riscv: rvv-0.9: add vcsr register, frank . chang, 2020/07/10
- Re: [RFC 06/65] target/riscv: rvv-0.9: add vcsr register,
Richard Henderson <=
- [RFC 14/65] target/riscv: rvv-0.9: stride load and store instructions, frank . chang, 2020/07/10
- [RFC 07/65] target/riscv: rvv-0.9: add vector context status, frank . chang, 2020/07/10
- [RFC 19/65] target/riscv: rvv-0.9: load/store whole register instructions, frank . chang, 2020/07/10
- [RFC 25/65] target/riscv: rvv-0.9: find-first-set mask bit instruction, frank . chang, 2020/07/10
- [RFC 31/65] target/riscv: rvv-0.9: whole register move instructions, frank . chang, 2020/07/10
- [RFC 02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64(), frank . chang, 2020/07/10