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[PATCH 09/11] riscv: Define riscv struct reginfo
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From: |
LIU Zhiwei |
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Subject: |
[PATCH 09/11] riscv: Define riscv struct reginfo |
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Date: |
Sun, 12 Jul 2020 00:16:53 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
risu_reginfo_riscv64.h | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
create mode 100644 risu_reginfo_riscv64.h
diff --git a/risu_reginfo_riscv64.h b/risu_reginfo_riscv64.h
new file mode 100644
index 0000000..4536480
--- /dev/null
+++ b/risu_reginfo_riscv64.h
@@ -0,0 +1,28 @@
+/******************************************************************************
+ * Copyright (c) 2020 T-Head Semiconductor Co., Ltd.
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the Eclipse Public License v1.0
+ * which accompanies this distribution, and is available at
+ * http://www.eclipse.org/legal/epl-v10.html
+ *
+ * Contributors:
+ * LIU Zhiwei(T-Head) - initial implementation
+ * based on Peter Maydell's risu_arm.c
+ *****************************************************************************/
+
+#ifndef RISU_REGINFO_RISCV64_H
+#define RISU_REGINFO_RISCV64_H
+
+struct reginfo {
+ uint64_t fault_address;
+ uint64_t regs[32];
+ uint64_t fregs[32];
+ uint64_t pc;
+ uint32_t flags;
+ uint32_t faulting_insn;
+
+ /* FP */
+ uint32_t fcsr;
+};
+
+#endif /* RISU_REGINFO_RISCV64_H */
--
2.23.0
- [PATCH 00/11] RISC-V risu porting, LIU Zhiwei, 2020/07/11
- [PATCH 02/11] riscv: Add RV64M instructions description, LIU Zhiwei, 2020/07/11
- [PATCH 04/11] riscv: Add RV64F instructions description, LIU Zhiwei, 2020/07/11
- [PATCH 05/11] riscv: Add RV64D instructions description, LIU Zhiwei, 2020/07/11
- [PATCH 06/11] riscv: Add RV64C instructions description, LIU Zhiwei, 2020/07/11
- [PATCH 08/11] riscv: Add standard test case, LIU Zhiwei, 2020/07/11
- [PATCH 10/11] riscv: Implement payload load interfaces, LIU Zhiwei, 2020/07/11
- [PATCH 11/11] riscv: Add configure script, LIU Zhiwei, 2020/07/11
- [PATCH 03/11] riscv: Add RV64A instructions description, LIU Zhiwei, 2020/07/11
- [PATCH 07/11] riscv: Generate payload scripts, LIU Zhiwei, 2020/07/11
- [PATCH 09/11] riscv: Define riscv struct reginfo,
LIU Zhiwei <=
- [PATCH 01/11] riscv: Add RV64I instructions description, LIU Zhiwei, 2020/07/11
- Re: [PATCH 00/11] RISC-V risu porting, LIU Zhiwei, 2020/07/21