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[RFC v2 05/76] target/riscv: fix return value of do_opivx_widen()
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From: |
frank . chang |
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Subject: |
[RFC v2 05/76] target/riscv: fix return value of do_opivx_widen() |
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Date: |
Wed, 22 Jul 2020 17:15:28 +0800 |
From: Frank Chang <frank.chang@sifive.com>
do_opivx_widen() should return false if check function returns false.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 7cd08f0868..c0b7375927 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1151,7 +1151,7 @@ static bool do_opivx_widen(DisasContext *s, arg_rmrr *a,
if (opivx_widen_check(s, a)) {
return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
}
- return true;
+ return false;
}
#define GEN_OPIVX_WIDEN_TRANS(NAME) \
--
2.17.1
- Re: [RFC v2 01/76] target/riscv: drop vector 0.7.1 support, (continued)
[RFC v2 02/76] target/riscv: rvv-0.9: support vector 0.9, frank . chang, 2020/07/22
[RFC v2 03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion, frank . chang, 2020/07/22
[RFC v2 04/76] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64(), frank . chang, 2020/07/22
[RFC v2 05/76] target/riscv: fix return value of do_opivx_widen(),
frank . chang <=
[RFC v2 06/76] target/riscv: fix vill bit index in vtype register, frank . chang, 2020/07/22
[RFC v2 07/76] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2020/07/22
[RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field, frank . chang, 2020/07/22
[RFC v2 09/76] target/riscv: rvv-0.9: add sstatus VS field, frank . chang, 2020/07/22
[RFC v2 10/76] target/riscv: rvv-0.9: add translation-time vector context status, frank . chang, 2020/07/22
[RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register, frank . chang, 2020/07/22