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[RFC v2 20/76] target/riscv: rvv-0.9: apply narrower nanbox helper in op
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From: |
frank . chang |
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Subject: |
[RFC v2 20/76] target/riscv: rvv-0.9: apply narrower nanbox helper in opfvf_trans |
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Date: |
Wed, 22 Jul 2020 17:15:43 +0800 |
From: Frank Chang <frank.chang@sifive.com>
If SEW < FLEN, call narrower_nanbox_fpr helper to generate the
correspond NaN-boxed value.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 22b4e11a20..85738ba4f7 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2196,7 +2196,18 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1,
uint32_t vs2,
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
- fn(dest, mask, cpu_fpr[rs1], src2, cpu_env, desc);
+ if ((s->sew < MO_64 && has_ext(s, RVD)) ||
+ (s->sew < MO_32)) {
+ /* SEW < FLEN */
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i32 sew = tcg_const_i32(1 << (s->sew + 3));
+ gen_helper_narrower_nanbox_fpr(t1, cpu_fpr[rs1], sew, cpu_env);
+ fn(dest, mask, t1, src2, cpu_env, desc);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i32(sew);
+ } else {
+ fn(dest, mask, cpu_fpr[rs1], src2, cpu_env, desc);
+ }
tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask);
--
2.17.1
- [RFC v2 16/76] target/riscv: rvv-0.9: add VMA and VTA, (continued)
- [RFC v2 20/76] target/riscv: rvv-0.9: apply narrower nanbox helper in opfvf_trans,
frank . chang <=
- [RFC v2 21/76] target/riscv: rvv-0.9: configure instructions, frank . chang, 2020/07/22
- [RFC v2 22/76] target/riscv: rvv-0.9: stride load and store instructions, frank . chang, 2020/07/22
- [RFC v2 23/76] target/riscv: rvv-0.9: index load and store instructions, frank . chang, 2020/07/22
- [RFC v2 24/76] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns, frank . chang, 2020/07/22
- [RFC v2 25/76] target/riscv: rvv-0.9: fault-only-first unit stride load, frank . chang, 2020/07/22
- [RFC v2 26/76] target/riscv: rvv-0.9: amo operations, frank . chang, 2020/07/22
- [RFC v2 27/76] target/riscv: rvv-0.9: load/store whole register instructions, frank . chang, 2020/07/22
- [RFC v2 28/76] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns, frank . chang, 2020/07/22