Re: [RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register

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Re: [RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register

From:	Richard Henderson
Subject:	Re: [RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register
Date:	Wed, 22 Jul 2020 09:58:57 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0

On 7/22/20 2:15 AM, frank.chang@sifive.com wrote:
> From: Greentime Hu <greentime.hu@sifive.com>
> 
> Signed-off-by: Greentime Hu <greentime.hu@sifive.com>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
>  target/riscv/cpu_bits.h | 1 +
>  target/riscv/csr.c      | 7 +++++++
>  2 files changed, 8 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

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Re: [RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field, (continued)
- [RFC v2 09/76] target/riscv: rvv-0.9: add sstatus VS field, frank . chang, 2020/07/22
  - Re: [RFC v2 09/76] target/riscv: rvv-0.9: add sstatus VS field, Richard Henderson, 2020/07/22
- [RFC v2 10/76] target/riscv: rvv-0.9: add translation-time vector context status, frank . chang, 2020/07/22
  - Re: [RFC v2 10/76] target/riscv: rvv-0.9: add translation-time vector context status, Richard Henderson, 2020/07/22
- [RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register, frank . chang, 2020/07/22
  - Re: [RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register, Richard Henderson, 2020/07/22
- [RFC v2 12/76] target/riscv: rvv-0.9: add vcsr register, frank . chang, 2020/07/22
  - Re: [RFC v2 12/76] target/riscv: rvv-0.9: add vcsr register, Richard Henderson, 2020/07/22
- [RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register, frank . chang, 2020/07/22
  - Re: [RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register, Richard Henderson <=
- [RFC v2 14/76] target/riscv: rvv-0.9: remove MLEN calculations, frank . chang, 2020/07/22
  - Re: [RFC v2 14/76] target/riscv: rvv-0.9: remove MLEN calculations, Richard Henderson, 2020/07/22
- [RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL, frank . chang, 2020/07/22
  - Re: [RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL, Richard Henderson, 2020/07/22
    - Re: [RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL, Frank Chang, 2020/07/22
- [RFC v2 16/76] target/riscv: rvv-0.9: add VMA and VTA, frank . chang, 2020/07/22
  - Re: [RFC v2 16/76] target/riscv: rvv-0.9: add VMA and VTA, Richard Henderson, 2020/07/22
    - Re: [RFC v2 16/76] target/riscv: rvv-0.9: add VMA and VTA, Frank Chang, 2020/07/22
- [RFC v2 17/76] target/riscv: rvv-0.9: update check functions, frank . chang, 2020/07/22
- [RFC v2 18/76] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2020/07/22

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