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Re: [RFC v2 42/76] target/riscv: rvv-0.9: whole register move instructio
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From: |
Richard Henderson |
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Subject: |
Re: [RFC v2 42/76] target/riscv: rvv-0.9: whole register move instructions |
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Date: |
Thu, 30 Jul 2020 13:14:20 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 7/22/20 2:16 AM, frank.chang@sifive.com wrote:
> + ((a->rd & ((LEN) - 1)) == 0) && \
QEMU_IS_ALIGNED(a->rd, LEN)
> + tcg_gen_gvec_mov(8, vreg_ofs(s, a->rd + i), \
> + vreg_ofs(s, a->rs2 + i), \
> + s->vlen / 8, s->vlen / 8); \
The first argument should be MO_8 (= 0) not 8.
You should have seen assertion failures with this.
There should be no reason to loop on this -- one move should be enough:
tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd),
vreg_ofs(s, a->rs2),
s->vlen / 8 * LEN, s->vlen / 8 * LEN);
If *that* asserts, because the length is too long or something, then I'll make
changes to tcg/tcg-op-gvec.c to make it work.
r~
- Re: [RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended, (continued)
- [RFC v2 38/76] target/riscv: rvv-0.9: register gather instructions, frank . chang, 2020/07/22
- [RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructions, frank . chang, 2020/07/22
- [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction, frank . chang, 2020/07/22
- [RFC v2 41/76] target/riscv: rvv-0.9: floating-point scalar move instructions, frank . chang, 2020/07/22
- [RFC v2 42/76] target/riscv: rvv-0.9: whole register move instructions, frank . chang, 2020/07/22
- Re: [RFC v2 42/76] target/riscv: rvv-0.9: whole register move instructions,
Richard Henderson <=
- [RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions, frank . chang, 2020/07/22
- [RFC v2 44/76] target/riscv: rvv-0.9: single-width averaging add and subtract instructions, frank . chang, 2020/07/22
- [RFC v2 45/76] target/riscv: rvv-0.9: single-width bit shift instructions, frank . chang, 2020/07/22
- [RFC v2 46/76] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow, frank . chang, 2020/07/22
- [RFC v2 47/76] target/riscv: rvv-0.9: narrowing integer right shift instructions, frank . chang, 2020/07/22