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Re: [PATCH v9 1/2] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_i
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From: |
dramforever |
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Subject: |
Re: [PATCH v9 1/2] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() |
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Date: |
Mon, 4 Jul 2022 10:36:28 +0800 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 |
On 7/4/22 10:17, Alistair Francis wrote:
> On Thu, Jun 30, 2022 at 4:13 PM Anup Patel <apatel@ventanamicro.com> wrote:
>> We should write transformed instruction encoding of the trapped
>> instruction in [m|h]tinst CSR at time of taking trap as defined
>> by the RISC-V privileged specification v1.12.
>>
>> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> @dramforever do you want to give an Ack or Reviewed-by?
>
> Alistair
Acked-By: dramforever <dramforever@live.com>
dramforever