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Re: [PATCH v10 05/12] target/riscv: Implement mcountinhibit CSR
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From: |
Atish Kumar Patra |
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Subject: |
Re: [PATCH v10 05/12] target/riscv: Implement mcountinhibit CSR |
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Date: |
Tue, 5 Jul 2022 00:47:23 -0700 |
On Mon, Jul 4, 2022 at 8:31 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
>
> 在 2022/6/21 上午7:15, Atish Patra 写道:
> > From: Atish Patra <atish.patra@wdc.com>
> >
> > As per the privilege specification v1.11, mcountinhibit allows to start/stop
> > a pmu counter selectively.
> >
> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > Signed-off-by: Atish Patra <atishp@rivosinc.com>
> > ---
> > target/riscv/cpu.h | 2 ++
> > target/riscv/cpu_bits.h | 4 ++++
> > target/riscv/csr.c | 25 +++++++++++++++++++++++++
> > target/riscv/machine.c | 1 +
> > 4 files changed, 32 insertions(+)
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index ffee54ea5c27..0a916db9f614 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -275,6 +275,8 @@ struct CPUArchState {
> > target_ulong scounteren;
> > target_ulong mcounteren;
> >
> > + target_ulong mcountinhibit;
> > +
> > target_ulong sscratch;
> > target_ulong mscratch;
> >
> > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > index 4d04b20d064e..b3f7fa713000 100644
> > --- a/target/riscv/cpu_bits.h
> > +++ b/target/riscv/cpu_bits.h
> > @@ -367,6 +367,10 @@
> > #define CSR_MHPMCOUNTER29 0xb1d
> > #define CSR_MHPMCOUNTER30 0xb1e
> > #define CSR_MHPMCOUNTER31 0xb1f
> > +
> > +/* Machine counter-inhibit register */
> > +#define CSR_MCOUNTINHIBIT 0x320
> > +
> > #define CSR_MHPMEVENT3 0x323
> > #define CSR_MHPMEVENT4 0x324
> > #define CSR_MHPMEVENT5 0x325
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index b4a8e15f498f..94d39a4ce1c5 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -1475,6 +1475,28 @@ static RISCVException write_mtvec(CPURISCVState
> > *env, int csrno,
> > return RISCV_EXCP_NONE;
> > }
> >
> > +static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno,
> > + target_ulong *val)
> > +{
> > + if (env->priv_ver < PRIV_VERSION_1_11_0) {
> > + return RISCV_EXCP_ILLEGAL_INST;
> > + }
> > +
>
> This seems can be done by add .min_priv_ver=PRIV_VERSION_1_11_0 in
> csr_ops table.
>
Yes. This can be dropped from both read/write_mcountihibit with min_priv_ver.
Thanks.
> Regards,
>
> Weiwei Li
>
> > + *val = env->mcountinhibit;
> > + return RISCV_EXCP_NONE;
> > +}
> > +
> > +static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
> > + target_ulong val)
> > +{
> > + if (env->priv_ver < PRIV_VERSION_1_11_0) {
> > + return RISCV_EXCP_ILLEGAL_INST;
> > + }
> > +
> > + env->mcountinhibit = val;
> > + return RISCV_EXCP_NONE;
> > +}
> > +
> > static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
> > target_ulong *val)
> > {
> > @@ -3745,6 +3767,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> > [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero },
> > [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero },
> >
> > + [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit,
> > + write_mcountinhibit
> > },
> > +
> > [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero },
> > [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero },
> > [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero },
> > diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> > index 2a437b29a1ce..87cd55bfd3a7 100644
> > --- a/target/riscv/machine.c
> > +++ b/target/riscv/machine.c
> > @@ -330,6 +330,7 @@ const VMStateDescription vmstate_riscv_cpu = {
> > VMSTATE_UINTTL(env.siselect, RISCVCPU),
> > VMSTATE_UINTTL(env.scounteren, RISCVCPU),
> > VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
> > + VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU),
> > VMSTATE_UINTTL(env.sscratch, RISCVCPU),
> > VMSTATE_UINTTL(env.mscratch, RISCVCPU),
> > VMSTATE_UINT64(env.mfromhost, RISCVCPU),
>