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Re: [PATCH V3 5/6] target/riscv: Fix checks in hmode/hmode32
From: |
Alistair Francis |
Subject: |
Re: [PATCH V3 5/6] target/riscv: Fix checks in hmode/hmode32 |
Date: |
Tue, 19 Jul 2022 09:10:15 +1000 |
On Mon, Jul 18, 2022 at 11:13 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Add check for the implicit dependence between H and S
>
> Csrs only existed in RV32 will not trigger virtual instruction fault
> when not in RV32 based on section 8.6.1 of riscv-privileged spec
> (draft-20220717)
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 5 +++++
> target/riscv/csr.c | 9 ++-------
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b8ce0959cb..455787a940 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -738,6 +738,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> return;
> }
>
> + if (cpu->cfg.ext_h && !cpu->cfg.ext_s) {
> + error_setg(errp, "H extension implicitly requires S-mode");
> + return;
> + }
> +
> if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
> error_setg(errp, "F extension requires Zicsr");
> return;
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 5c69dc838c..cf15aa67b7 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -311,8 +311,7 @@ static int aia_smode32(CPURISCVState *env, int csrno)
>
> static RISCVException hmode(CPURISCVState *env, int csrno)
> {
> - if (riscv_has_ext(env, RVS) &&
> - riscv_has_ext(env, RVH)) {
> + if (riscv_has_ext(env, RVH)) {
> /* Hypervisor extension is supported */
> if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
> env->priv == PRV_M) {
> @@ -328,11 +327,7 @@ static RISCVException hmode(CPURISCVState *env, int
> csrno)
> static RISCVException hmode32(CPURISCVState *env, int csrno)
> {
> if (riscv_cpu_mxl(env) != MXL_RV32) {
> - if (!riscv_cpu_virt_enabled(env)) {
> - return RISCV_EXCP_ILLEGAL_INST;
> - } else {
> - return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
> - }
> + return RISCV_EXCP_ILLEGAL_INST;
> }
>
> return hmode(env, csrno);
> --
> 2.17.1
>
>
- [PATCH V3 0/6] Improve the U/S/H extension related check, Weiwei Li, 2022/07/18
- [PATCH V3 4/6] target/riscv: Add check for csrs existed with U extension, Weiwei Li, 2022/07/18
- [PATCH V3 5/6] target/riscv: Fix checks in hmode/hmode32, Weiwei Li, 2022/07/18
- Re: [PATCH V3 5/6] target/riscv: Fix checks in hmode/hmode32,
Alistair Francis <=
- [PATCH V3 1/6] target/riscv: Add check for supported privilege mode combinations, Weiwei Li, 2022/07/18
- [PATCH V3 3/6] target/riscv: Fix checkpatch warning may triggered in csr_ops table, Weiwei Li, 2022/07/18
- [PATCH V3 6/6] target/riscv: Simplify the check in hmode to resue the check in riscv_csrrw_check, Weiwei Li, 2022/07/18
- [PATCH V3 2/6] target/riscv: H extension depends on I extension, Weiwei Li, 2022/07/18
- Re: [PATCH V3 0/6] Improve the U/S/H extension related check, Alistair Francis, 2022/07/18