[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH qemu v6 05/10] target/riscv: rvv: Add mask agnostic for vecto
From: |
Alistair Francis |
Subject: |
Re: [PATCH qemu v6 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions |
Date: |
Thu, 21 Jul 2022 10:16:31 +1000 |
On Mon, Jun 20, 2022 at 5:08 PM ~eopxd <eopxd@git.sr.ht> wrote:
>
> From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
>
> Signed-off-by: eop Chen <eop.chen@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 1 +
> target/riscv/vector_helper.c | 10 ++++++++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 83b85bb851..e6aa5295a1 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1718,6 +1718,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
> \
> data = FIELD_DP32(data, VDATA, VTA, s->vta); \
> data = \
> FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
> + data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> vreg_ofs(s, a->rs1), \
> vreg_ofs(s, a->rs2), cpu_env, \
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index d1daa764b7..07ce671879 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -1404,12 +1404,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
> *vs2, \
> uint32_t vl = env->vl; \
> uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
> uint32_t vta_all_1s = vext_vta_all_1s(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
> ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + if (vma) { \
> + vext_set_elem_mask(vd, i, 1); \
> + } \
> continue; \
> } \
> vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \
> @@ -1462,11 +1467,16 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong
> s1, void *vs2, \
> uint32_t vl = env->vl; \
> uint32_t total_elems = env_archcpu(env)->cfg.vlen; \
> uint32_t vta_all_1s = vext_vta_all_1s(desc); \
> + uint32_t vma = vext_vma(desc); \
> uint32_t i; \
> \
> for (i = env->vstart; i < vl; i++) { \
> ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
> if (!vm && !vext_elem_mask(v0, i)) { \
> + /* set masked-off elements to 1s */ \
> + if (vma) { \
> + vext_set_elem_mask(vd, i, 1); \
> + } \
> continue; \
> } \
> vext_set_elem_mask(vd, i, \
> --
> 2.34.2
>
>
[Prev in Thread] |
Current Thread |
[Next in Thread] |
- Re: [PATCH qemu v6 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions,
Alistair Francis <=