Re: [PATCH qemu v6 00/10] Add mask agnostic behavior for rvv instructions

[Alistair Francis]

On Mon, Jun 20, 2022 at 4:56 PM ~eopxd <eopxd@git.sr.ht> wrote:
>
> According to v-spec, mask agnostic behavior can be either kept as
> undisturbed or set elements' bits to all 1s. To distinguish the
> difference of mask policies, QEMU should be able to simulate the mask
> agnostic behavior as "set mask elements' bits to all 1s".
>
> There are multiple possibility for agnostic elements according to
> v-spec. The main intent of this patch-set tries to add option that
> can distinguish between mask policies. Setting agnostic elements to
> all 1s allows QEMU to express this.
>
> The following instructions that are always unmasked and not affected:
>
> - Vector add-with-carry and subtract-with-borrow instructions
> - Vector merge and move instructions
> - Vector reduction instructions
> - Vector mask-register logical instructions
> - `vcompress`
>
> v2 updates:
> - Rebase upon changes of the tail agnostic patch-set
> - Minor change for vector load/store instructions
>
> v3 updates:
> - Rebase upon changes of the tail agnostic patch-set
> - Fix coding style, add missing space
> - Trigger `vma` when encountering vector load instructions and not in
>   vector stores
>
> v4 updates:
> - Rebase upon changes of the tail agnostic patch-set
>
> v5 updates:
> - Tag WeiWei as Reviewed-by for this patch-set
>
> v6 updates:
> - Now that the tail agnostic patch-set has been merged, this
>   patch-set no longer depends on it. Rebased to latest master.
>
> Yueh-Ting (eop) Chen (9):
>   target/riscv: rvv: Add mask agnostic for vv instructions
>   target/riscv: rvv: Add mask agnostic for vector load / store
>     instructions
>   target/riscv: rvv: Add mask agnostic for vx instructions
>   target/riscv: rvv: Add mask agnostic for vector integer shift
>     instructions
>   target/riscv: rvv: Add mask agnostic for vector integer comparison
>     instructions
>   target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic
>     instructions
>   target/riscv: rvv: Add mask agnostic for vector floating-point
>     instructions
>   target/riscv: rvv: Add mask agnostic for vector mask instructions
>   target/riscv: rvv: Add mask agnostic for vector permutation
>     instructions
>
> eopXD (1):
>   target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask
>     agnostic behavior

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.c                      |   1 +
>  target/riscv/cpu.h                      |   2 +
>  target/riscv/cpu_helper.c               |   2 +
>  target/riscv/insn_trans/trans_rvv.c.inc |  28 +++++
>  target/riscv/internals.h                |   5 +-
>  target/riscv/translate.c                |   2 +
>  target/riscv/vector_helper.c            | 152 ++++++++++++++++++++----
>  7 files changed, 167 insertions(+), 25 deletions(-)
>
> --
> 2.34.2
>