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[PATCH v6 08/12] target/riscv: Update the next rule addr in pmpaddr_csr_
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From: |
Weiwei Li |
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Subject: |
[PATCH v6 08/12] target/riscv: Update the next rule addr in pmpaddr_csr_write() |
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Date: |
Wed, 17 May 2023 17:15:15 +0800 |
Currently only the rule addr of the same index of pmpaddr is updated
when pmpaddr CSR is modified. However, the rule addr of next PMP entry
may also be affected if its A field is PMP_AMATCH_TOR. So we should
also update it in this case.
Write to pmpaddr CSR will not affect the rule nums, So we needn't update
call pmp_update_rule_nums() in pmpaddr_csr_write().
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 8cb8519b0c..efe72afe29 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -507,6 +507,7 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t
addr_index,
target_ulong val)
{
trace_pmpaddr_csr_write(env->mhartid, addr_index, val);
+ bool is_next_cfg_tor = false;
if (addr_index < MAX_RISCV_PMPS) {
/*
@@ -515,9 +516,9 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t
addr_index,
*/
if (addr_index + 1 < MAX_RISCV_PMPS) {
uint8_t pmp_cfg = env->pmp_state.pmp[addr_index + 1].cfg_reg;
+ is_next_cfg_tor = PMP_AMATCH_TOR == pmp_get_a_field(pmp_cfg);
- if (pmp_cfg & PMP_LOCK &&
- PMP_AMATCH_TOR == pmp_get_a_field(pmp_cfg)) {
+ if (pmp_cfg & PMP_LOCK && is_next_cfg_tor) {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpaddr write - pmpcfg + 1 locked\n");
return;
@@ -526,7 +527,10 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t
addr_index,
if (!pmp_is_locked(env, addr_index)) {
env->pmp_state.pmp[addr_index].addr_reg = val;
- pmp_update_rule(env, addr_index);
+ pmp_update_rule_addr(env, addr_index);
+ if (is_next_cfg_tor) {
+ pmp_update_rule_addr(env, addr_index + 1);
+ }
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpaddr write - locked\n");
--
2.25.1
- [PATCH v6 00/12] target/riscv: Fix PMP related problem, Weiwei Li, 2023/05/17
- [PATCH v6 04/12] target/riscv: Change the return type of pmp_hart_has_privs() to bool, Weiwei Li, 2023/05/17
- [PATCH v6 06/12] target/riscv: Remove unused paramters in pmp_hart_has_privs_default(), Weiwei Li, 2023/05/17
- [PATCH v6 07/12] target/riscv: Flush TLB when MMWP or MML bits are changed, Weiwei Li, 2023/05/17
- [PATCH v6 01/12] target/riscv: Update pmp_get_tlb_size(), Weiwei Li, 2023/05/17
- [PATCH v6 03/12] target/riscv: Make the short cut really work in pmp_hart_has_privs, Weiwei Li, 2023/05/17
- [PATCH v6 05/12] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled, Weiwei Li, 2023/05/17
- [PATCH v6 02/12] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp, Weiwei Li, 2023/05/17
- [PATCH v6 08/12] target/riscv: Update the next rule addr in pmpaddr_csr_write(),
Weiwei Li <=
- [PATCH v6 09/12] target/riscv: Flush TLB when pmpaddr is updated, Weiwei Li, 2023/05/17
- [PATCH v6 10/12] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes, Weiwei Li, 2023/05/17
- [PATCH v6 12/12] target/riscv: Deny access if access is partially inside the PMP entry, Weiwei Li, 2023/05/17
- [PATCH v6 11/12] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write, Weiwei Li, 2023/05/17
- Re: [PATCH v6 00/12] target/riscv: Fix PMP related problem, Alistair Francis, 2023/05/18